Invention Grant
- Patent Title: Wafer level package structure and the fabrication method thereof
- Patent Title (中): 晶圆级封装结构及其制造方法
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Application No.: US13205864Application Date: 2011-08-09
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Publication No.: US08642385B2Publication Date: 2014-02-04
- Inventor: Yan Xun Xue , Ping Huang , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Ming-Chen Lu
- Applicant: Yan Xun Xue , Ping Huang , Yueh-Se Ho , Hamza Yilmaz , Jun Lu , Ming-Chen Lu
- Applicant Address: US CA Sunnyvale
- Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee: Alpha & Omega Semiconductor, Inc.
- Current Assignee Address: US CA Sunnyvale
- Agency: C H Emily LLC
- Agent Chein-Hwa Tsao
- Main IPC: H01L23/498
- IPC: H01L23/498 ; H01L21/78

Abstract:
The present invention proposes a package for semiconductor device and the fabrication method for integrally encapsulating a whole semiconductor chip within a molding compound. In the semicondcutor device package, bonding pads distributed on the top of the chip are redistributed into an array of redistributed bonding pads located in an dielectric layer by utilizing the redistribution technique. The electrodes or signal terminals on the top of the semiconductor chip are connected to an electrode metal segment on the bottom of the chip by conductive materials filled in through holes formed in a silicon substrate of a semiconductor wafer. Furthermore, the top molding portion and the bottom molding portion seal the semiconductor chip completely, thus providing optimum mechanical and electrical protections.
Public/Granted literature
- US20130037935A1 WAFER LEVEL PACKAGE STRUCTURE AND THE FABRICATION METHOD THEREOF Public/Granted day:2013-02-14
Information query
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