发明授权
- 专利标题： Methods for forming interconnect structures for integration of multi-layered integrated circuit devices
- 专利标题（中）： 形成用于集成多层集成电路器件的互连结构的方法
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申请号： US13085122申请日： 2011-04-12
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公开(公告)号： US08664112B2公开(公告)日： 2014-03-04
- 发明人: Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
- 申请人： Gurtej S. Sandhu , Nishant Sinha , John A. Smythe
- 申请人地址： US ID Boise
- 专利权人： Micron Technology, Inc.
- 当前专利权人： Micron Technology, Inc.
- 当前专利权人地址： US ID Boise
- 代理机构： TraskBritt
- 主分类号： H01L23/52
- IPC分类号： H01L23/52
摘要：
Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.