公开(公告)号：US08664112B2

公开(公告)日：2014-03-04

申请号：US13085122

申请日：2011-04-12

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L23/52

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US20110195547A1

公开(公告)日：2011-08-11

申请号：US13085122

申请日：2011-04-12

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US20100013107A1

公开(公告)日：2010-01-21

申请号：US12174393

申请日：2008-07-16

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US07928577B2

公开(公告)日：2011-04-19

申请号：US12174393

申请日：2008-07-16

申请人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

发明人： Gurtej S. Sandhu ,  Nishant Sinha ,  John A. Smythe

IPC分类号： H01L23/52

CPC分类号： H01L23/5283 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/5329 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/105 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices comprise at least one integrated circuit layer, at least one conductive trace and an insulative material adjacent at least a portion of the at least one conductive trace. At least one interconnect structure extends through a portion of the at least one conductive trace and a portion of the insulative material, the at least one interconnect structure comprising a transverse cross-sectional dimension through the at least one conductive trace which differs from a transverse cross-sectional dimension through the insulative material. Methods of forming semiconductor devices comprising at least one interconnect structure are also disclosed.

摘要翻译： 半导体器件包括至少一个集成电路层，至少一个导电迹线和与至少一个导电迹线的至少一部分相邻的绝缘材料。 至少一个互连结构延伸穿过所述至少一个导电迹线的一部分和所述绝缘材料的一部分，所述至少一个互连结构包括穿过所述至少一个导电迹线的横向截面尺寸，所述导电迹线与横向交叉不同 通过绝缘材料的尺寸。 还公开了形成包括至少一个互连结构的半导体器件的方法。

公开(公告)号：US08129289B2

公开(公告)日：2012-03-06

申请号：US11543515

申请日：2006-10-05

申请人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

发明人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

IPC分类号： H01L21/00

CPC分类号： H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

公开(公告)号：US08598560B1

公开(公告)日：2013-12-03

申请号：US13547270

申请日：2012-07-12

申请人： Marko Milojevic ,  John A. Smythe ,  Gurtej S. Sandhu

发明人： Marko Milojevic ,  John A. Smythe ,  Gurtej S. Sandhu

IPC分类号： H01L29/00 ,  H01L29/02 ,  H01L29/04 ,  H01L47/00 ,  H01L21/8236 ,  G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0011 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/143 ,  H01L45/144 ,  H01L45/145 ,  H01L45/146

摘要： A resistive memory element comprising a conductive material, an active material over the conductive material, and an ion source material on the active material and comprising at least one chalcogen, at least one active metal, and at least one additional element. Additional resistive memory elements, as well as methods of forming resistive memory elements, and related resistive memory cells and resistive memory devices are also described.

摘要翻译： 一种电阻式存储元件，包括导电材料，导电材料上的活性材料和活性材料上的离子源材料，并且包含至少一种硫族元素，至少一种活性金属和至少一种附加元素。 还描述了额外的电阻性存储器元件，以及形成电阻性存储器元件的方法，以及相关的电阻式存储器单元和电阻式存储器件。

公开(公告)号：US20080085612A1

公开(公告)日：2008-04-10

申请号：US11543515

申请日：2006-10-05

申请人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

发明人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

IPC分类号： H01L21/469

CPC分类号： H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

公开(公告)号：US06849510B2

公开(公告)日：2005-02-01

申请号：US10667919

申请日：2003-09-22

申请人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

发明人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

摘要： Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

摘要翻译： 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

公开(公告)号：US08241944B2

公开(公告)日：2012-08-14

申请号：US12830079

申请日：2010-07-02

申请人： Joseph N. Greeley ,  John A. Smythe

发明人： Joseph N. Greeley ,  John A. Smythe

IPC分类号： H01L21/00

CPC分类号： H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

摘要翻译： 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。

公开(公告)号：US08735211B2

公开(公告)日：2014-05-27

申请号：US13517747

申请日：2012-06-14

申请人： Joseph N. Greeley ,  John A. Smythe

发明人： Joseph N. Greeley ,  John A. Smythe

IPC分类号： H01L21/00

CPC分类号： H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

摘要翻译： 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。