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37 条记录 (耗时 0.018 秒)

    Trench isolation implantation
    1.
    发明授权
    Trench isolation implantation 有权
    沟槽隔离植入

    公开(公告)号：US08686535B2

    公开(公告)日：2014-04-01

    申请号：US12758488

    申请日：2010-04-12

    申请人： Gurtej S. Sandhu ,  John A. Smythe, III

    发明人： Gurtej S. Sandhu ,  John A. Smythe, III

    IPC分类号： H01L21/70

    CPC分类号： H01L21/76237 ,  G11C11/401 ,  H01L27/10844 ,  H01L27/11517

    摘要： Embodiments of the disclosure include a shallow trench isolation structure having a dielectric material with energetic species implanted to a predetermined depth of the dielectric material. Embodiments further include methods of fabricating the trench structures with the implant of energetic species to the predetermined depth. In various embodiments the implant of energetic species is used to densify the dielectric material to provide a uniform wet etch rate across the surface of the dielectric material. Embodiments also include memory devices, integrated circuits, and electronic systems that include shallow trench isolation structures having the dielectric material with the high flux of energetic species implanted to the predetermined depth of the dielectric material.

    摘要翻译： 本公开的实施例包括浅沟槽隔离结构，其具有将能量物质注入电介质材料的预定深度的电介质材料。 实施例还包括使能量物质的植入物到预定深度制造沟槽结构的方法。 在各种实施例中，能量物质的注入用于致密化电介质材料，以提供穿过电介质材料表面的均匀的湿蚀刻速率。 实施例还包括存储器件，集成电路和电子系统，其包括浅沟槽隔离结构，其具有植入到介电材料的预定深度的高能量物质的高通量的电介质材料。

    Method to deposit conformal low temperature SiO2
    3.
    发明授权
    Method to deposit conformal low temperature SiO2 有权
    沉积保温低温SiO2的方法

    公开(公告)号：US08129289B2

    公开(公告)日：2012-03-06

    申请号：US11543515

    申请日：2006-10-05

    申请人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    发明人： John A. Smythe ,  Gurtej S. Sandhu ,  Brian J. Coppa ,  Shyam Surthi ,  Shuang Meng

    IPC分类号： H01L21/00

    CPC分类号： H01L21/3088 ,  H01L21/02164 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/3086 ,  H01L21/3141 ,  H01L21/31612

    摘要： Methods of controlling critical dimensions of reduced-sized features during semiconductor fabrication through pitch multiplication are disclosed. Pitch multiplication is accomplished by patterning mask structures via conventional photoresist techniques and subsequently transferring the pattern to a sacrificial material. Spacer regions are then formed on the vertical surfaces of the transferred pattern following the deposition of a conformal material via atomic layer deposition. The spacer regions, and therefore the reduced features, are then transferred to a semiconductor substrate.

    摘要翻译： 公开了通过间距倍增来控制半导体制造期间尺寸减小的特征的关键尺寸的方法。 间距倍增通过通过常规光致抗蚀剂技术图案化掩模结构并随后将图案转移到牺牲材料来实现。 然后通过原子层沉积沉积保形材料之后，在转印图案的垂直表面上形成间隔区。 然后将间隔区域以及因此减小的特征转移到半导体衬底。

    Isolation trench
    4.
    发明授权
    Isolation trench 有权
    隔离槽

    公开(公告)号：US07622769B2

    公开(公告)日：2009-11-24

    申请号：US11497665

    申请日：2006-08-01

    申请人： John A. Smythe, III ,  Jigish D. Trivedi

    发明人： John A. Smythe, III ,  Jigish D. Trivedi

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76224

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, an oxygen barrier is deposited into the trench. An expandable, oxidizable liner, preferably amorphous silicon, is then deposited. The trench is then filled with a spin-on dielectric (SOD) material. A densification process is then applied, whereby the SOD material contracts and the oxidizable liner expands. Preferably, the temperature is ramped up while oxidizing during at least part of the densification process. The resulting trench has a negligible vertical wet etch rate gradient and a negligible recess at the top of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，将氧势垒沉积到沟槽中。 然后沉积可膨胀的可氧化衬垫，优选非晶硅。 然后用旋涂电介质（SOD）材料填充沟槽。 然后施加致密化过程，由此SOD材料收缩并且可氧化衬里膨胀。 优选地，在致密化过程的至少部分期间，温度升高而氧化。 所形成的沟槽具有可忽略的垂直湿蚀刻速率梯度和在沟槽顶部的可忽略的凹陷。

    Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base
    5.
    发明授权
    Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base 有权
    沟槽绝缘结构包括沿着沟槽的壁比沿底部更薄的氧化物衬垫

    公开(公告)号：US07271463B2

    公开(公告)日：2007-09-18

    申请号：US11009665

    申请日：2004-12-10

    申请人： John A. Smythe, III ,  William Budge

    发明人： John A. Smythe, III ,  William Budge

    IPC分类号： H01L23/58

    CPC分类号： H01L21/76224

    摘要： A method of depositing dielectric material into sub-micron spaces and resultant structures is provided. After a trench is etched in the surface of a wafer, a liner layer preferably is deposited into the trench. An anisotropic plasma process is then performed on the trench. A silicon layer may be deposited on the base of the trench during the plasma process, or the plasma can treat the liner layer. The trench is then filled with a spin-on precursor. A densification or reaction process is then applied to convert the spin-on material into an insulator, and oxidizing the silicon rich layer on the base of the trench. The resulting trench has a consistent etch rate from top to bottom of the trench.

    摘要翻译： 提供了将电介质材料沉积到亚微米空间和结构中的方法。 在晶片的表面中蚀刻沟槽之后，衬垫层优选沉积到沟槽中。 然后在沟槽上进行各向异性等离子体处理。 在等离子体工艺期间，硅层可以沉积在沟槽的基底上，或等离子体可以处理衬层。 然后用旋涂前体填充沟槽。 然后施加致密化或反应过程以将旋涂材料转化成绝缘体，并且氧化沟槽底部的富硅层。 所得到的沟槽具有从沟槽的顶部到底部的一致的蚀刻速率。

    Non-oxidizing spacer densification method for manufacturing semiconductor devices
    6.
    发明授权
    Non-oxidizing spacer densification method for manufacturing semiconductor devices 有权
    用于制造半导体器件的非氧化间隔物致密化方法

    公开(公告)号：US06849510B2

    公开(公告)日：2005-02-01

    申请号：US10667919

    申请日：2003-09-22

    申请人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

    发明人： Brett D. Lowe ,  John A. Smythe ,  Timothy K. Carns

    IPC分类号： H01L21/8238 ,  H01L21/8234

    CPC分类号： H01L21/823842 ,  H01L21/823864 ,  H01L21/823878

    摘要： Non-oxidizing spacer densification method for producing semiconductor devices, such as MOSFET devices, and that may be implemented during semiconductor fabrication with little or substantially no polycide adhesion loss experienced during spacer densification. The method may be implemented to provide good polycide adhesion characteristics with reduced process complexity over conventional methods by eliminating the need for additional process steps such as metal silicide encapsulation or polysilicon surface treatments.

    摘要翻译： 用于制造半导体器件（例如MOSFET器件）的非氧化间隔物致密化方法，并且可以在半导体制造期间实施，在间隔物致密化期间几乎没有或基本上没有聚硅氧烷粘附损失。 该方法可以实现以通过消除对附加工艺步骤（例如金属硅化物封装或多晶硅表面处理）的需要来提供优于常规方法的降低的工艺复杂性的良好的多晶硅化合物附着特性。

    Resistive RAM devices and methods
    9.
    发明授权
    Resistive RAM devices and methods 有权
    电阻式RAM器件和方法

    公开(公告)号：US08241944B2

    公开(公告)日：2012-08-14

    申请号：US12830079

    申请日：2010-07-02

    申请人： Joseph N. Greeley ,  John A. Smythe

    发明人： Joseph N. Greeley ,  John A. Smythe

    IPC分类号： H01L21/00

    CPC分类号： H01L45/1683 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1633

    摘要： The present disclosure includes a high density resistive random access memory (RRAM) device, as well as methods of fabricating a high density RRAM device. One method of forming an RRAM device includes forming a resistive element having a metal-metal oxide interface. Forming the resistive element includes forming an insulative material over the first electrode, and forming a via in the insulative material. The via is conformally filled with a metal material, and the metal material is planarized to within the via. A portion of the metal material within the via is selectively treated to create a metal-metal oxide interface within the via. A second electrode is formed over the resistive element.

    摘要翻译： 本公开包括高密度电阻随机存取存储器（RRAM）装置，以及制造高密度RRAM装置的方法。 形成RRAM器件的一种方法包括形成具有金属 - 金属氧化物界面的电阻元件。 形成电阻元件包括在第一电极上形成绝缘材料，以及在绝缘材料中形成通孔。 通孔由金属材料共形填充，并且金属材料被平坦化到通孔内。 通孔内的金属材料的一部分被选择性地处理以在通孔内产生金属 - 金属氧化物界面。 第二电极形成在电阻元件上。