Invention Grant
US08664712B2 Flash memory cell on SeOI having a second control gate buried under the insulating layer
有权
SeOI上的闪存单元具有埋在绝缘层之下的第二控制栅极
- Patent Title: Flash memory cell on SeOI having a second control gate buried under the insulating layer
- Patent Title (中): SeOI上的闪存单元具有埋在绝缘层之下的第二控制栅极
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Application No.: US12946135Application Date: 2010-11-15
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Publication No.: US08664712B2Publication Date: 2014-03-04
- Inventor: Carlos Mazure , Richard Ferrant
- Applicant: Carlos Mazure , Richard Ferrant
- Applicant Address: FR Bernin
- Assignee: Soitec
- Current Assignee: Soitec
- Current Assignee Address: FR Bernin
- Agency: Winston & Strawn LLP
- Priority: FR0958746 20091208
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/788 ; H01L27/12 ; H01L21/336 ; H01L21/3205 ; H01L21/4763
Abstract:
The invention relates to a flash memory cell having a FET transistor with a floating gate on a semiconductor-on-insulator (SOI) substrate composed of a thin film of semiconductor material separated from a base substrate by an insulating buried oxide (BOX) layer, The transistor has in the thin film, a channel, with two control gates, a front control gate located above the floating gate and separated from it by an inter-gate dielectric, and a back control gate located within the base substrate directly under the insulating (BOX) layer and separated from the channel by only the insulating (BOX) layer. The two control gates are designed to be used in combination to perform a cell programming operation. The invention also relates to a memory array made up of a plurality of memory cells according to the first aspect of the invention, which can be in an array of rows and columns, and a method of fabricating such memory cells and memory arrays.
Public/Granted literature
- US20110134698A1 FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER Public/Granted day:2011-06-09
Information query
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