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发明授权
US08667196B2 Interconnect congestion reduction for memory-mapped peripherals 有权
内存映射外围设备的互连拥塞减少

Interconnect congestion reduction for memory-mapped peripherals
摘要：
A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.
摘要（中）：

提供了一种用于映射一个或多个从设备之间的地址和多层互连系统中的至少一个对应的主设备的方法和设备，该多层互连系统包括用于在一个或多个从设备与主设备之间进行接口的多个总线矩阵。 所述方法和装置可操作用于接收对应于系统的地址映射，通过至少一个总线矩阵接收关于一个或多个从属设备的连通性的信息，确定主设备是否具有多于一个与之相关的默认从单元， 并且当所述主设备具有多于一个与之相关联的默认从单元时，产生第一和第二地址映射，并且将所述系统配置为每个主设备具有不超过一个默认从单元。

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