Invention Grant
US08683281B2 Scan path delay testing with two memories and three subdivisions
有权
扫描路径延迟测试与两个存储器和三个细分
- Patent Title: Scan path delay testing with two memories and three subdivisions
- Patent Title (中): 扫描路径延迟测试与两个存储器和三个细分
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Application No.: US13708237Application Date: 2012-12-07
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Publication No.: US08683281B2Publication Date: 2014-03-25
- Inventor: Lee D. Whetsel , Joel J. Graber
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28
Abstract:
Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present disclosure improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.
Public/Granted literature
- US20130097468A1 LOW POWER SCAN & DELAY TEST METHOD AND APPARATUS Public/Granted day:2013-04-18
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