Invention Grant
- Patent Title: Stacked die semiconductor package
- Patent Title (中): 堆叠芯片半导体封装
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Application No.: US13490451Application Date: 2012-06-06
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Publication No.: US08692387B2Publication Date: 2014-04-08
- Inventor: Shunan Qiu , Guoliang Gong , Xuesong Xu , Xingshou Pang , Beiyue Yan , Yinghui Li
- Applicant: Shunan Qiu , Guoliang Gong , Xuesong Xu , Xingshou Pang , Beiyue Yan , Yinghui Li
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Priority: CN201110205715 20110722
- Main IPC: H01L23/31
- IPC: H01L23/31
Abstract:
A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.
Public/Granted literature
- US20130020690A1 STACKED DIE SEMICONDUCTOR PACKAGE Public/Granted day:2013-01-24
Information query
IPC分类:
