公开(公告)号：US08692387B2

公开(公告)日：2014-04-08

申请号：US13490451

申请日：2012-06-06

申请人： Shunan Qiu ,  Guoliang Gong ,  Xuesong Xu ,  Xingshou Pang ,  Beiyue Yan ,  Yinghui Li

发明人： Shunan Qiu ,  Guoliang Gong ,  Xuesong Xu ,  Xingshou Pang ,  Beiyue Yan ,  Yinghui Li

IPC分类号： H01L23/31

CPC分类号： H01L23/3135 ,  H01L21/56 ,  H01L21/568 ,  H01L23/31 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/05554 ,  H01L2224/06134 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4846 ,  H01L2224/49171 ,  H01L2224/49177 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2924/01029 ,  H01L2924/10162 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/078 ,  H01L2924/00

摘要： A semiconductor package and method of assembling a semiconductor package includes encapsulating a first pre-packaged semiconductor die stacked on top of and interconnected with a second semiconductor die. The first packaged semiconductor die is positioned and fixed relative to a lead frame with a temporary carrier such as tape. The second semiconductor die is attached and interconnected directly to the first packaged semiconductor die and lead frame. The interconnected first packaged die and second semiconductor die, and lead frame are encapsulated to form the semiconductor package. Different types of semiconductor packages such as quad flat no-lead (QFN) and ball grid array (BGA) may be formed, which provide increased input/output (I/O) count and functionality.

摘要翻译： 半导体封装和组装半导体封装的方法包括封装堆叠在第二半导体管芯的顶部并与第二半导体管芯互连的第一预先封装的半导体管芯。 第一封装半导体管芯相对于具有诸如带的临时载体的引线框定位和固定。 第二半导体管芯被连接并直接连接到第一封装半导体管芯和引线框架。 互连的第一封装管芯和第二半导体管芯以及引线框架被封装以形成半导体封装。 可以形成不同类型的半导体封装，例如四边形无引线（QFN）和球栅阵列（BGA），其提供增加的输入/输出（I / O）计数和功能。

公开(公告)号：US08643153B2

公开(公告)日：2014-02-04

申请号：US13461801

申请日：2012-05-02

申请人： Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

发明人： Shunan Qiu ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

IPC分类号： H01L23/495 ,  H01L23/48

CPC分类号： H01L23/49555 ,  H01L21/4842 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

摘要翻译： 一种用于组装半导体器件的方法包括提供具有天然平面的引线框架和具有天然引线间距的多个引线。 该过程包括修剪和形成多个引线的第一子集以提供第一行引线。 该过程包括修剪和形成多个引线的第二子集以提供第二排引线。 引线的至少一个子集以相对于天平平面的钝角形成，使得与引线的第一或第二子集相关联的引线间距大于原始引线间距。

公开(公告)号：US20120286406A1

公开(公告)日：2012-11-15

申请号：US13461801

申请日：2012-05-02

申请人： Shunan QIU ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

发明人： Shunan QIU ,  Zhigang Bai ,  Xuesong Xu ,  Beiyue Yan ,  You Ge

IPC分类号： H01L23/495 ,  H01L21/00

CPC分类号： H01L23/49555 ,  H01L21/4842 ,  H01L2924/0002 ,  H01L2924/00

摘要： A process for assembling a semiconductor device includes providing a lead frame having a native plane and a plurality of leads having a native lead pitch. The process includes trimming and forming a first subset of the plurality of leads to provide a first row of leads. The process includes trimming and forming a second subset of the plurality of leads to provide a second row of leads. At least one subset of leads is formed with an obtuse angle relative to the native plane such that lead pitch associated with the first or second subset of leads is greater than the native lead pitch.

摘要翻译： 一种用于组装半导体器件的方法包括提供具有天然平面的引线框架和具有天然引线间距的多个引线。 该过程包括修剪和形成多个引线的第一子集以提供第一行引线。 该过程包括修剪和形成多个引线的第二子集以提供第二排引线。 引线的至少一个子集以相对于天平平面的钝角形成，使得与引线的第一或第二子集相关联的引线间距大于原始引线间距。