发明授权
US08700943B2 Controlling time stamp counter (TSC) offsets for mulitple cores and threads
有权
控制多个内核和线程的时间戳计数器（TSC）偏移量
- 专利标题： Controlling time stamp counter (TSC) offsets for mulitple cores and threads
- 专利标题（中）： 控制多个内核和线程的时间戳计数器（TSC）偏移量
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申请号： US12644989申请日： 2009-12-22
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公开(公告)号： US08700943B2公开(公告)日： 2014-04-15
- 发明人: Martin G. Dixon , Jeremy J. Shrall , Rajesh S. Parthasarathy
- 申请人： Martin G. Dixon , Jeremy J. Shrall , Rajesh S. Parthasarathy
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Trop, Pruner & Hu, P.C.
- 主分类号： G06F1/12
- IPC分类号： G06F1/12 ; G06F15/16
摘要：
In one embodiment, the present invention includes a method for recording a time stamp counter (TSC) value of a first TSC counter of a processor before a system suspension, accessing the stored TSC value after the system suspension, and directly updating a thread offset value associated with a first thread executing on a first core of the processor with the stored TSC value, without performing a synchronization between a plurality of cores of the processor. Other embodiments are described and claimed.
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