发明授权
US08719819B2 Mechanism for instruction set based thread execution on a plurality of instruction sequencers
有权
基于多个指令定序器的基于指令集的线程执行的机制
- 专利标题： Mechanism for instruction set based thread execution on a plurality of instruction sequencers
- 专利标题（中）： 基于多个指令定序器的基于指令集的线程执行的机制
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申请号： US11173326申请日： 2005-06-30
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公开(公告)号： US08719819B2公开(公告)日： 2014-05-06
- 发明人: Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
- 申请人： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
- 申请人地址： US CA Santa Clara
- 专利权人： Intel Corporation
- 当前专利权人： Intel Corporation
- 当前专利权人地址： US CA Santa Clara
- 代理机构： Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号： G06F9/46
- IPC分类号： G06F9/46
摘要：
In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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