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公开(公告)号：US08479217B2
公开(公告)日：2013-07-02
申请号：US13221119
申请日：2011-08-30
Applicant: Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju V. Patel , Jason W. Brandt , Anil Aggarwal , John L. Reid
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof.
Abstract translation: 本发明的实施例提供了一种基于在操作系统可见定序器上运行并使用指令集扩展的操作系统调度的线程来创建持久用户级线程在操作系统隔离上运行的方法 音序器独立于操作系统调度线程上的上下文切换活动。 操作系统调度的线程和持久用户级线程可以共享公共虚拟地址空间。 本发明的实施例还可以提供一种使服务线程在附加操作系统可见定序器上运行以向持久用户级线程提供操作系统服务的方法。 本发明的实施例还可以提供其装置，系统和机器可读介质。
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2.发明申请MECHANISM FOR INSTRUCTION SET BASED THREAD EXECUTION ON A PLURALITY OF INSTRUCTION SEQUENCERS 审中-公开用于指导性设计的机构执行多个指令序列公开(公告)号：US20130054940A1
公开(公告)日：2013-02-28
申请号：US13608970
申请日：2012-09-10
Applicant: Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
Inventor： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
IPC: G06F9/312
CPC classification number: G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
Abstract translation: 在一个实施例中，提供了一种方法。 该方法包括响应于在应用级程序的控制下对第二指令定序器执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有1）引用一个或多个指令定序器的字段，或者2）使用指向代码执行代码时特定寻址一个或多个指令定序器的代码的指针进行隐式引用。
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3.发明授权System and method for selecting optimal processor performance levels by using processor hardware feedback mechanisms 有权通过使用处理器硬件反馈机制来选择最佳处理器性能水平的系统和方法公开(公告)号：US07917789B2
公开(公告)日：2011-03-29
申请号：US11864800
申请日：2007-09-28
Applicant: Russell J. Fenger , Anil Aggarwal , Shiv Kaushik
Inventor： Russell J. Fenger , Anil Aggarwal , Shiv Kaushik
IPC: G06F1/08
CPC classification number: G06F1/3203 , G06F1/3243 , Y02D10/126 , Y02D10/152
Abstract: An embodiment of the present invention is a system and method relating to adaptive power management using hardware feedback to select optimal processor frequencies and reduce power/watt. In at least one embodiment, the present invention is intended to optimize processor frequency and power/watt usage based on the hardware feedback and processor stall behavior.
Abstract translation: 本发明的一个实施例是涉及使用硬件反馈的自适应功率管理以选择最佳处理器频率并降低功率/功率的系统和方法。 在至少一个实施例中，本发明旨在基于硬件反馈和处理器失速行为来优化处理器频率和功率/瓦特使用。
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公开(公告)号：US20080148027A1
公开(公告)日：2008-06-19
申请号：US11638700
申请日：2006-12-14
Applicant: Russell J. Fenger , Anil Aggarwal , Efraim Rotem
Inventor： Russell J. Fenger , Anil Aggarwal , Efraim Rotem
IPC: G06F9/06
CPC classification number: G06F1/3203 , G06F1/324 , Y02D10/126
Abstract: Briefly, a processor and a method of setting a performance state of a turbo mode enabled processor. The method includes determining an effective performance state over a predetermined time period, calculating a target performance state based on core utilization and the effective performance state over the predetermined time period and setting the turbo mode enabled processor to a turbo mode performance state.
Abstract translation: 简而言之，是一种处理器和一种设置turbo模式使能处理器的性能状态的方法。 该方法包括在预定时间段内确定有效性能状态，在预定时间段内基于核心利用率和有效性能状态计算目标性能状态，并将启用turbo模式的处理器设置为turbo模式执行状态。
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公开(公告)号：US07213093B2
公开(公告)日：2007-05-01
申请号：US10608708
申请日：2003-06-27
Applicant: Per Hammarlund , James B. Crossland , Anil Aggarwal , Shivnandan D. Kaushik
Inventor： Per Hammarlund , James B. Crossland , Anil Aggarwal , Shivnandan D. Kaushik
CPC classification number: G06F9/526 , G06F1/3203 , G06F9/3004 , G06F9/30083 , G06F9/30087 , G06F9/3851
Abstract: A method, apparatus, and system are provided for monitoring locks using monitor-memory wait. According to one embodiment, a node associated with a contended lock is monitored; and a processor seeking the contended lock is put to sleep until a monitor event occurs.
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Patent Agency Ranking
公开(公告)号：US20070079301A1
公开(公告)日：2007-04-05
申请号：US11239475
申请日：2005-09-30
Applicant: Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju Patel , Jason Brandt , Anil Aggarwal , John Reid
Inventor： Gautham Chinya , Hong Wang , Prashant Sethi , Shivnandan Kaushik , Bryant Bigbee , John Shen , Richard Hankins , Xiang Zou , Baiju Patel , Jason Brandt , Anil Aggarwal , John Reid
IPC: G06F9/45
CPC classification number: G06F9/3005 , G06F9/3009 , G06F9/3851 , G06F9/3861 , G06F9/3877 , G06F9/3885 , G06F9/461
Abstract: Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of context switch activities on the operating-system-scheduled thread. The operating-system-scheduled thread and the persistent user-level thread may share a common virtual address space. Embodiments of the invention may also provide a method of causing a service thread running on an additional operating-system-visible sequencer to provide operating system services to the persistent user-level thread. Embodiments of the invention may further provide apparatus, system, and machine-readable medium thereof
Abstract translation: 本发明的实施例提供了一种基于在操作系统可见定序器上运行并使用指令集扩展的操作系统调度的线程来创建持久用户级线程在操作系统隔离上运行的方法 音序器独立于操作系统调度线程上的上下文切换活动。 操作系统调度的线程和持久用户级线程可以共享公共虚拟地址空间。 本发明的实施例还可以提供一种使服务线程在附加操作系统可见定序器上运行以向持久用户级线程提供操作系统服务的方法。 本发明的实施例还可以提供其装置，系统和机器可读介质
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7.发明申请Mechanism to emulate user-level multithreading on an OS-sequestered sequencer 有权在操作系统隔离的音序器上模拟用户级多线程的机制公开(公告)号：US20060150183A1
公开(公告)日：2006-07-06
申请号：US11026597
申请日：2004-12-30
Applicant: Gautham Chinya , Hong Wang , Xiang Zou , James Held , Prashant Sethi , Trung Diep , Anil Aggarwal , Baiju Patel , Shiv Kaushik , Bryant Bigbee , John Shen , Richard Hankins , John Reid
Inventor： Gautham Chinya , Hong Wang , Xiang Zou , James Held , Prashant Sethi , Trung Diep , Anil Aggarwal , Baiju Patel , Shiv Kaushik , Bryant Bigbee , John Shen , Richard Hankins , John Reid
IPC: G06F9/46
CPC classification number: G06F9/45533 , G06F9/4881
Abstract: Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the abstraction layer provides sequestration logic, proxy execution logic, transition detection and shred suspension logic, and sequencer arithmetic logic. Other embodiments are also described and claimed.
Abstract translation: 方法，装置和系统实施例，用于通过用于包括从操作系统控制隔离的一个或多个定序器的系统的抽象层来提供用户级别创建，控制和同步OS不可见的“碎片”。 对于至少一个实施例，抽象层提供封存逻辑，代理执行逻辑，转换检测和分片挂起逻辑以及定序器算术逻辑。 还描述和要求保护其他实施例。
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8.发明授权公开(公告)号：US09720697B2
公开(公告)日：2017-08-01
申请号：US13608970
申请日：2012-09-10
Applicant: Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
Inventor： Hong Wang , John Shen , Ed Grochowski , James Paul Held , Bryant Bigbee , Shivnandan D. Kaushik , Gautham Chinya , Xiang Zou , Per Hammarlund , Xinmin Tian , Anil Aggarwal , Scott Dion Rodgers , Prashant Sethi , Baiju V. Patel , Richard Andrew Hankins
CPC classification number: G06F9/3867 , G06F9/30003 , G06F9/30043 , G06F9/3005 , G06F9/3009 , G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3851 , G06F9/4843 , G06F9/4881
Abstract: In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.
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公开(公告)号：US08984199B2
公开(公告)日：2015-03-17
申请号：US10631522
申请日：2003-07-31
Applicant: Per Hammarlund , James B. Crossland , Shivnandan D. Kaushik , Anil Aggarwal
Inventor： Per Hammarlund , James B. Crossland , Shivnandan D. Kaushik , Anil Aggarwal
CPC classification number: G06F9/4812 , G06F9/544
Abstract: According to an embodiment of the invention, a method and apparatus for inter-processor interrupts in a multi-processor system are described. An embodiment comprises writing an inter-processor interrupt request to a first memory location; monitoring the first memory location; detecting the inter-processor interrupt request in the first memory location; calling a function for the inter-processor interrupt request; and performing the function for the inter-processor interrupt request.
Abstract translation: 根据本发明的实施例，描述了用于多处理器系统中的处理器间中断的方法和装置。 一个实施例包括将处理器间中断请求写入第一存储器位置; 监控第一个内存位置; 检测第一存储器位置中的处理器间中断请求; 调用处理器间中断请求的功能; 并执行处理器间中断请求的功能。
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10.发明申请MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开多核处理器的不对称计算元素之间的迁移任务公开(公告)号：US20140129808A1
公开(公告)日：2014-05-08
申请号：US13994142
申请日：2012-04-27
Applicant: Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
Inventor： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC: G06F9/30
CPC classification number: G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
Abstract: In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
Abstract translation: 在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。 可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。 描述和要求保护其他实施例。
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