发明授权
US08735302B2 High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction
有权
高生产率组合氧化物梯度和PVD / ALD金属沉积结合光刻用于栅极功能提取
- 专利标题: High productivity combinatorial oxide terracing and PVD/ALD metal deposition combined with lithography for gate work function extraction
- 专利标题(中): 高生产率组合氧化物梯度和PVD / ALD金属沉积结合光刻用于栅极功能提取
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申请号: US13480023申请日: 2012-05-24
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公开(公告)号: US08735302B2公开(公告)日: 2014-05-27
- 发明人: Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
- 申请人: Amol Joshi , John Foster , Zhendong Hong , Olov Karlsson , Bei Li , Usha Raghuram
- 申请人地址: US CA San Jose
- 专利权人: Intermolecular, Inc.
- 当前专利权人: Intermolecular, Inc.
- 当前专利权人地址: US CA San Jose
- 主分类号: H01L21/31
- IPC分类号: H01L21/31 ; H01L21/469
摘要:
Metal gate high-k capacitor structures with lithography patterning are used to extract gate work function using a combinatorial workflow. Oxide terracing, together with high productivity combinatorial process flow for metal deposition can provide optimum high-k gate dielectric and metal gate solutions for high performance logic transistors. The high productivity combinatorial technique can provide an evaluation of effective work function for given high-k dielectric metal gate stacks for PMOS and NMOS transistors, which is critical in identifying and selecting the right materials.
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