发明授权
US08754530B2 Self-aligned borderless contacts for high density electronic and memory device integration
有权
用于高密度电子和存储器件集成的自对准无边界触点
- 专利标题： Self-aligned borderless contacts for high density electronic and memory device integration
- 专利标题（中）： 用于高密度电子和存储器件集成的自对准无边界触点
-
申请号： US12193339申请日： 2008-08-18
-
公开(公告)号： US08754530B2公开(公告)日： 2014-06-17
- 发明人: Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
- 申请人： Katherina E. Babich , Josephine B. Chang , Nicholas C. Fuller , Michael A. Guillorn , Isaac Lauer , Michael J. Rooks
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 代理机构： Fleit Gibbons Gutman Bongini & Bianco PL
- 代理商 Thomas Grzesik
- 主分类号： H01L23/48
- IPC分类号： H01L23/48
摘要：
A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.