公开(公告)号：US08241957B2

公开(公告)日：2012-08-14

申请号：US12906690

申请日：2010-10-18

申请人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

发明人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01R12/00 ,  H01R4/58

CPC分类号： B81B3/0035 ,  H01L2924/0002 ,  Y10T428/249986 ,  H01L2924/00

摘要： A method for fabricating a negative thermal expanding system device includes coating a wafer with a thermally decomposable polymer, patterning the decomposable polymer into repeating disk patterns, releasing the decomposable polymer from the wafer and forming a sheet of repeating patterned disks, suspending the sheet into a first solution with seeding compounds for electroless decomposition, removing the sheet from the first solution, suspending the sheet into a second solution to electrolessly deposit a first layer material onto the sheet, removing the sheet from the second solution, suspending the sheet into a third solution to deposit a second layer of material having a lower TCE value than the first layer of material, separating the patterned disks from one another, and annealing thermally the patterned disks to decompose the decomposable polymer and creating a cavity in place of the decomposable polymer.

摘要翻译： 一种制造负热膨胀系统装置的方法包括用可热分解的聚合物涂覆晶片，将可分解的聚合物图案化成重复的圆盘图案，将可分解的聚合物从晶片上释放出来并形成一张重复图案的圆盘，将薄片悬挂在 用于无电解分解的接种化合物的第一溶液，从第一溶液中除去片材，将片材悬浮在第二溶液中以将第一层材料无电沉积到片材上，从第二溶液中除去片材，将片材悬浮在第三溶液中 沉积具有比第一层材料低的TCE值的第二层材料，将图案化的盘彼此分离，并对图案化的盘进行热退火以分解可分解聚合物并产生空腔以代替可分解的聚合物。

公开(公告)号：US08008095B2

公开(公告)日：2011-08-30

申请号：US11866455

申请日：2007-10-03

申请人： Solomon Assefa ,  Gregory Costrini ,  Christopher Vincent Jahnes ,  Michael J. Rooks ,  Jonathan Zanhong Sun

发明人： Solomon Assefa ,  Gregory Costrini ,  Christopher Vincent Jahnes ,  Michael J. Rooks ,  Jonathan Zanhong Sun

IPC分类号： H01L21/00

CPC分类号： H01L43/12

摘要： A pillar structure that is contacted by a vertical contact is formed in an integrated circuit. A hard mask is formed and utilized to pattern a least a portion of the pillar structure. The hard mask comprises carbon. Subsequently, the hard mask is removed. A conductive material is then deposited in a region previously occupied by the hard mask to form the vertical contact. The hard mask may, for example, comprise diamond-like carbon. The pillar structure may have a width or diameter less than about 100 nanometers.

摘要翻译： 在集成电路中形成由垂直接触件接触的柱结构。 硬掩模被形成并用于对柱结构的至少一部分进行图案化。 硬掩模包含碳。 随后，去除硬掩模。 然后将导电材料沉积在先前由硬掩模占据的区域中以形成垂直接触。 硬掩模可以例如包括类金刚石碳。 柱结构可以具有小于约100纳米的宽度或直径。

公开(公告)号：US20090212388A1

公开(公告)日：2009-08-27

申请号：US12436189

申请日：2009-05-06

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L29/06

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target. The structure including a first trench in a semiconductor substrate, the first trench extending from a top surface of the substrate into the substrate a first distance; an electron back-scattering layer in a bottom of the first trench; a dielectric capping layer in the trench over the back-scattering layer; and a second trench in the substrate, the second trench extending from the top surface of the substrate into the substrate a second distance, the second distance less than the first distance.

摘要翻译： 用于将集成电路芯片的制造级别的第一组特征对准到电子束对准目标的结构。 所述结构包括半导体衬底中的第一沟槽，所述第一沟槽从所述衬底的顶表面延伸到所述衬底中第一距离; 在第一沟槽的底部的电子背散射层; 背面散射层上的沟槽中的介电覆盖层; 以及所述衬底中的第二沟槽，所述第二沟槽从所述衬底的顶表面延伸到所述衬底中第二距离，所述第二距离小于所述第一距离。

公开(公告)号：US08445892B2

公开(公告)日：2013-05-21

申请号：US13554065

申请日：2012-07-20

申请人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

发明人： Guy Cohen ,  Conal E. Murray ,  Michael J. Rooks

IPC分类号： H01L29/775

CPC分类号： H01L29/78696 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/7848 ,  H01L29/785

摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

公开(公告)号：US08153494B2

公开(公告)日：2012-04-10

申请号：US12541371

申请日：2009-08-14

申请人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

发明人： Jack O. Chu ,  Guy M. Cohen ,  John A. Ott ,  Michael J. Rooks ,  Paul M. Solomon

IPC分类号： H01L21/336

CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/458 ,  H01L29/7839 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78684 ,  H01L29/78696

摘要： A FET structure with a nanowire forming the FET channel, and doped source and drain regions formed by radial epitaxy from the nanowire body is disclosed. A top gated and a bottom gated nanowire FET structures are discussed. The source and drain fabrication can use either selective or non-selective epitaxy.

摘要翻译： 公开了具有形成FET沟道的纳米线的FET结构以及由纳米线体径向外延形成的掺杂源极和漏极区。 讨论了顶盖门控和底部门控纳米线FET结构。 源极和漏极制造可以使用选择性或非选择性外延。

公开(公告)号：US07696057B2

公开(公告)日：2010-04-13

申请号：US11618974

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L21/76

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到包括形成在衬底中的高原子重量层并且使用电子束光刻形成第一组特征的电子束对准靶的方法， 将集成电路芯片的相同制造级别的特征集合到形成在基板中的光学对准目标并且使用光刻形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。

公开(公告)号：US07572499B2

公开(公告)日：2009-08-11

申请号：US11044777

申请日：2005-01-26

申请人： Zvonimir Z. Bandic ,  A. David Erpelding ,  Jordan Asher Katine ,  Quang Le ,  Kim Y. Lee ,  Jui-Lung Li ,  Michael J. Rooks

发明人： Zvonimir Z. Bandic ,  A. David Erpelding ,  Jordan Asher Katine ,  Quang Le ,  Kim Y. Lee ,  Jui-Lung Li ,  Michael J. Rooks

IPC分类号： G11B5/64 ,  G11B5/66 ,  G11B5/65 ,  G11B5/86

CPC分类号： G11B5/865 ,  G11B5/855 ,  Y10T428/24612

摘要： A contact magnetic transfer (CMT) master template has a flexible plastic film with a planarized top or upper surface containing magnetic islands separated from one another by nonmagnetic regions. The flexible plastic film is secured at its perimeter to a silicon annulus that provides rigid support at the perimeter of the film. The plastic film is preferably polyimide that has recesses filled with the magnetic material that form the pattern of magnetic islands. The upper surfaces of the islands and the upper surfaces of the nonmagnetic regions form a continuous planar surface. The nonmagnetic regions are formed of chemical-mechanical-polishing (CMP) stop layer material that remains after a CMP process has planarized the upper surface of the plastic film.

摘要翻译： 接触磁传递（CMT）主模板具有柔性塑料膜，其具有包含通过非磁性区域彼此分离的磁岛的平坦化顶部或上部表面。 柔性塑料膜在其周边固定在硅环上，该硅环在膜的周边提供刚性支撑。 塑料膜优选为具有填充有形成磁岛图案的磁性材料的凹部的聚酰亚胺。 岛的上表面和非磁性区的上表面形成连续的平坦表面。 非磁性区域由化学机械抛光（CMP）阻挡层材料形成，其在CMP工艺已经使塑料膜的上表面平坦化之后残留。

公开(公告)号：US07417315B2

公开(公告)日：2008-08-26

申请号：US10310532

申请日：2002-12-05

申请人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

发明人： Gareth Geoffrey Hougham ,  S. Jay Chey ,  James Patrick Doyle ,  Xiao Hu Liu ,  Christopher V. Jahnes ,  Paul Alfred Lauro ,  Nancy C. LaBianca ,  Michael J. Rooks

IPC分类号： H01L21/302 ,  B32B5/22 ,  G02B26/00

CPC分类号： B81B3/0035 ,  H01L2924/0002 ,  Y10T428/249986 ,  H01L2924/00

摘要： A Negative Thermal Expansion system (NTEs) device for TCE compensation or CTE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging. One aspect of the present invention provides a method for fabricating micromachine devices that have negative thermal expansion coefficients that can be made into a composite for manipulation of the TCE of the material. These devices and composites made with these devices are in the categories of materials called “smart materials” or “responsive materials.” Another aspect of the present invention provides microdevices comprised of dual opposed bilayers of material where the two bilayers are attached to one another at the peripheral edges only, and where the bilayers themselves are at a minimum stress conditions at a reference temperature defined by the temperature at which the bilayers are formed. These devices have the technologically useful property of volumetrically expanding upon lowering of the device temperature below the reference or processing temperature.

摘要翻译： 用于微电子封装中弹性体复合材料和导电弹性体互连的TCE补偿或CTE补偿的负热膨胀系统（NTE）装置。 本发明的一个方面提供了一种用于制造具有负热膨胀系数的微机械装置的方法，该热膨胀系数可以制成用于操纵材料的TCE的复合材料。 这些设备和这些设备制成的复合材料属于称为“智能材料”或“响应材料”的材料类别。 本发明的另一方面提供了由双重相对的双层材料构成的微器件，其中两个双层仅在外围边缘处彼此附接，并且其中双层本身处于由温度定义的参考温度下的最小应力条件 双层形成。 当器件温度降低到参考温度或加工温度以下时，这些器件具有技术上有用的特性。

公开(公告)号：US20080157260A1

公开(公告)日：2008-07-03

申请号：US11618974

申请日：2007-01-02

申请人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

发明人： David Michael Fried ,  John Michael Hergenrother ,  Sharee Jane McNab ,  Michael J. Rooks ,  Anna Topol

IPC分类号： H01L23/544 ,  G03F7/20 ,  H01L21/76

CPC分类号： G03F9/708 ,  B82Y10/00 ,  B82Y40/00 ,  G03F7/7045 ,  G03F9/7076 ,  G03F9/7088 ,  H01J37/3174 ,  H01L21/76283 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for aligning a first set of features of a fabrication level of an integrated circuit chip to an electron beam alignment target including a high atomic weight layer formed in a substrate and forming the first set of features using electron beam lithography and for aligning a second set of features of the same fabrication level of the integrated circuit chip to an optical alignment target formed in the substrate and forming the second set of features using photolithography, the optical alignment target itself is aligned to the electron beam alignment target. Also a method of forming and a structure of the electron beam alignment target.

摘要翻译： 一种用于将集成电路芯片的制造级别的第一组特征对准到包括形成在衬底中的高原子重量层并且使用电子束光刻形成第一组特征的电子束对准靶的方法， 将集成电路芯片的相同制造级别的特征集合到形成在基板中的光学对准目标并且使用光刻形成第二组特征，所述光学对准目标本身与电子束对准目标对准。 还有一种形成电子束对准靶的方法和结构。

公开(公告)号：US07160477B2

公开(公告)日：2007-01-09

申请号：US11044288

申请日：2005-01-26

申请人： Zvonimir Z. Bandic ,  A. David Erpelding ,  Jordan Asher Katine ,  Quang Le ,  Kim Y. Lee ,  Jui-Lung Li ,  Michael J. Rooks

发明人： Zvonimir Z. Bandic ,  A. David Erpelding ,  Jordan Asher Katine ,  Quang Le ,  Kim Y. Lee ,  Jui-Lung Li ,  Michael J. Rooks

IPC分类号： B44C1/22

CPC分类号： G11B5/865 ,  B82Y10/00 ,  C23F3/04 ,  C23F4/00 ,  G11B5/72 ,  G11B5/743 ,  G11B5/82 ,  G11B5/855 ,  Y10T29/4903 ,  Y10T29/49032

摘要： A contact magnetic transfer (CMT) master template is made by first adhering a plastic film to a first surface of a silicon wafer. A resist pattern is then formed on the polyimide film and the polyimide is reactive-ion-etched through the resist to form recesses. The resist is removed and a chemical-mechanical-polishing (CMP) stop layer is deposited over the non-recessed regions of the polyimide, and optionally into the bottoms of the recesses. A layer of magnetic material is then deposited over the polyimide film to fill the recesses. A CMP process is then performed to remove magnetic material above the recesses and above the non-recessed regions and continued until the CMP stop layer is reached. The resulting upper surface of the polyimide film is then a continuous planar film of magnetic islands and regions of CMP stop layer material that function as the nonmagnetic regions of the template.

摘要翻译： 通过首先将塑料膜粘附到硅晶片的第一表面上来制造接触磁传递（CMT）主模板。 然后在聚酰亚胺膜上形成抗蚀剂图案，并通过抗蚀剂反应离子蚀刻聚酰亚胺以形成凹陷。 去除抗蚀剂，并在化学机械抛光（CMP）停止层上沉积在聚酰亚胺的非凹陷区域上，并且任选地沉积到凹部的底部中。 然后将一层磁性材料沉积在聚酰亚胺膜上以填充凹部。 然后执行CMP处理以除去凹部上方的磁性材料并且在非凹陷区域上方并继续直到达到CMP停止层。 所得到的聚酰亚胺膜的上表面是磁性岛的连续平面膜和作为模板的非磁性区域的CMP停止层材料的区域。