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发明授权
US08754530B2 Self-aligned borderless contacts for high density electronic and memory device integration 有权
用于高密度电子和存储器件集成的自对准无边界触点

Self-aligned borderless contacts for high density electronic and memory device integration
摘要：
A method for fabricating a transistor having self-aligned borderless electrical contacts is disclosed. A gate stack is formed on a silicon region. An off-set spacer is formed surrounding the gate stack. A sacrificial layer that includes a carbon-based film is deposited overlying the silicon region, the gate stack, and the off-set spacer. A pattern is defined in the sacrificial layer to define a contact area for the electrical contact. The pattern exposes at least a portion of the gate stack and source/drain. A dielectric layer is deposited overlying the sacrificial layer that has been patterned and the portion of the gate stack that has been exposed. The sacrificial layer that has been patterned is selectively removed to define the contact area at the height that has been defined. The contact area for the height that has been defined is metalized to form the electrical contact.
摘要（中）：

公开了一种制造具有自对准无边界电触头的晶体管的方法。 栅极堆叠形成在硅区域上。 在栅堆叠周围形成偏置的间隔物。 包括碳基膜的牺牲层沉积在硅区域，栅极堆叠和偏置间隔物上。 在牺牲层中限定图案以限定电接触的接触面积。 该图案暴露了栅极堆叠和源极/漏极的至少一部分。 沉积覆盖已经图案化的牺牲层和已经暴露的栅极堆叠的部分的电介质层。 已经图案化的牺牲层被选择性地去除以限定已经定义的高度处的接触面积。 已经定义的高度的接触面积被金属化以形成电接触。

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