发明授权
US08765559B2 Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material
有权
通过盖层去除形成的复杂的栅极电极结构,并减少嵌入的应变诱导半导体材料的损耗
- 专利标题: Sophisticated gate electrode structures formed by cap layer removal with reduced loss of embedded strain-inducing semiconductor material
- 专利标题(中): 通过盖层去除形成的复杂的栅极电极结构,并减少嵌入的应变诱导半导体材料的损耗
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申请号: US13358101申请日: 2012-01-25
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公开(公告)号: US08765559B2公开(公告)日: 2014-07-01
- 发明人: Stephan Kronholz , Gunda Beernink , Markus Lenski , Frank Seliger , Frank Richter
- 申请人: Stephan Kronholz , Gunda Beernink , Markus Lenski , Frank Seliger , Frank Richter
- 申请人地址: KY Grand Cayman
- 专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人: GLOBALFOUNDRIES Inc.
- 当前专利权人地址: KY Grand Cayman
- 代理机构: Amerson Law Firm, PLLC
- 优先权: DE102011003385 20110131
- 主分类号: H01L21/336
- IPC分类号: H01L21/336
摘要:
When forming sophisticated gate electrode structures, such as high-k metal gate electrode structures, an appropriate encapsulation may be achieved, while also undue material loss of a strain-inducing semiconductor material that is provided in one type of transistor may be avoided. To this end, the patterning of the protective spacer structure prior to depositing the strain-inducing semiconductor material may be achieved for each type of transistor on the basis of the same process flow, while, after the deposition of the strain-inducing semiconductor material, an etch stop layer may be provided so as to preserve integrity of the active regions.
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