Invention Grant
- Patent Title: Variable interconnect geometry for electronic packages and fabrication methods
- Patent Title (中): 用于电子封装和制造方法的可变互连几何
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Application No.: US11805693Application Date: 2007-05-24
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Publication No.: US08766449B2Publication Date: 2014-07-01
- Inventor: Suresh K. Sitaraman , Karan Kacker , Thomas Sokol
- Applicant: Suresh K. Sitaraman , Karan Kacker , Thomas Sokol
- Applicant Address: US GA Atlanta
- Assignee: Georgia Tech Research Corporation
- Current Assignee: Georgia Tech Research Corporation
- Current Assignee Address: US GA Atlanta
- Agency: Thomas|Horstemeyer, LLP.
- Main IPC: H01L23/532
- IPC: H01L23/532

Abstract:
Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.
Public/Granted literature
- US20080245559A1 Variable interconnect geometry for electronic packages and fabrication methods Public/Granted day:2008-10-09
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