公开(公告)号：US08766449B2

公开(公告)日：2014-07-01

申请号：US11805693

申请日：2007-05-24

Applicant: Suresh K. Sitaraman ,  Karan Kacker ,  Thomas Sokol

Inventor： Suresh K. Sitaraman ,  Karan Kacker ,  Thomas Sokol

IPC: H01L23/532

CPC classification number: H01R13/2407 ,  H01L23/3114 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  Y10T29/49224 ,  H01L2924/00015 ,  H01L2924/00

Abstract: Disclosed is a variable interconnect geometry formed on a substrate that allows for increased electrical performance of the interconnects without compromising mechanical reliability. The compliance of the interconnects varies from the center of the substrate to edges of the substrate. The variation in compliance can either be step-wise or continuous. Exemplary low-compliance interconnects include columnar interconnects and exemplary high-compliance interconnects include helix interconnects. A cost-effective implementation using batch fabrication of the interconnects at a wafer level through sequential lithography and electroplating processes may be employed.

Abstract translation: 公开了形成在基板上的可变互连几何形状，其允许互连的增加的电性能而不损害机械可靠性。 互连的顺应性从基板的中心到基板的边缘不同。 顺应性的变化可以是逐步的还是连续的。 示例性的低顺应性互连包括柱状互连，并且示例性的高符合性互连包括螺旋互连。 可以使用通过顺序光刻和电镀工艺在晶片级上批量制造互连的成本有效的实现。

公开(公告)号：US09099458B2

公开(公告)日：2015-08-04

申请号：US13539480

申请日：2012-07-01

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H01L23/498 ,  H05K3/46 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing supporting the plurality of stacked vias. The platted through hole landing includes an etched pattern.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括支撑多个堆叠的通孔的平板通孔平台。 镀层通孔着色包括蚀刻图案。

公开(公告)号：US08866026B2

公开(公告)日：2014-10-21

申请号：US13569826

申请日：2012-08-08

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K1/11 ,  H05K1/09 ,  H05K3/46 ,  H01L23/498 ,  H05K1/02

CPC classification number: H01L23/49827 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05548 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/0969 ,  Y10T29/49155 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A stacked via structure for reducing vertical stiffness includes: a plurality of stacked vias, each via disposed on a disc-like structure. The disc-like structure includes a platted through hole landing with a thickness of substantially 3 μm. The platted through hole landing includes an etched pattern and a copper top surface.

Abstract translation: 用于减小垂直刚度的堆叠通孔结构包括：多个堆叠的通孔，每个通孔设置在盘状结构上。 盘状结构包括厚度基本为3μm的板状通孔着落。 镀层通孔着色包括蚀刻图案和铜顶表面。

公开(公告)号：US08206160B2

公开(公告)日：2012-06-26

申请号：US12152149

申请日：2008-05-13

Applicant: Karan Kacker ,  Suresh K. Sitaraman

Inventor： Karan Kacker ,  Suresh K. Sitaraman

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/4092 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.

Abstract translation: 公开了包括耦合在电触点之间并且允许增加的电性能而不损害机械可靠性的单路径和多路径兼容互连的装置。 示例性设备包括在第一端处耦合到电触点的导电垂直锚固件; 以及一个或多个导电弓形梁，其在第一端处耦合到垂直锚的第二端，并且在第二端处耦合到第二电触点。 一个电触点包括裸片接触焊盘，另一个电触点包括基板接触焊盘。 或者，一个电触点包括基板接触焊盘，另一个电触头包括印刷电路板接触垫。 而且，一个电触头包括裸片接触焊盘，另一个电触点包括印刷电路板接触垫。 还公开了制造该装置的方法。

公开(公告)号：US20090189290A1

公开(公告)日：2009-07-30

申请号：US12020565

申请日：2008-01-27

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09609 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4919 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.

Abstract translation: 用于衬底/芯片组件中的堆叠通孔的衬底通孔结构包括：中心通孔堆叠和多个堆叠的通孔，围绕中心通过堆叠聚集。 在这种结构中，中心通孔和周围的通孔由铜制成。 一些周围的通孔可以是非功能通孔，并且它们可以具有与功能通孔不同的高度。

公开(公告)号：US20080305653A1

公开(公告)日：2008-12-11

申请号：US12152149

申请日：2008-05-13

Applicant: Karan Kacker ,  Suresh K. Sitaraman

Inventor： Karan Kacker ,  Suresh K. Sitaraman

IPC: H01R12/36 ,  H01R43/16

CPC classification number: H01R13/2407 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/4092 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.

Abstract translation: 公开了包括耦合在电触点之间并且允许增加的电性能而不损害机械可靠性的单路径和多路径兼容互连的装置。 示例性设备包括在第一端处耦合到电触点的导电垂直锚固件; 以及一个或多个导电弓形梁，其在第一端处耦合到垂直锚的第二端，并且在第二端处耦合到第二电触点。 一个电触点包括裸片接触焊盘，另一个电触点包括基板接触焊盘。 或者，一个电触点包括基板接触焊盘，另一个电触头包括印刷电路板接触垫。 而且，一个电触头包括裸片接触焊盘，另一个电触点包括印刷电路板接触垫。 还公开了制造该装置的方法。

公开(公告)号：US08382489B2

公开(公告)日：2013-02-26

申请号：US13435977

申请日：2012-03-30

Applicant: Karan Kacker ,  Suresh K. Sitaraman

Inventor： Karan Kacker ,  Suresh K. Sitaraman

IPC: H01R12/00

CPC classification number: H01R13/2407 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/4092 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.

Abstract translation: 公开了包括耦合在电触点之间并且允许增加的电性能而不损害机械可靠性的单路径和多路径兼容互连的装置。 示例性设备包括在第一端处耦合到电触点的导电垂直锚固件; 以及一个或多个导电弓形梁，其在第一端处耦合到垂直锚的第二端，并且在第二端处耦合到第二电触点。 一个电触点包括裸片接触焊盘，另一个电触点包括基板接触焊盘。 或者，一个电触点包括基板接触焊盘，另一个电触头包括印刷电路板接触垫。 而且，一个电触头包括裸片接触焊盘，另一个电触点包括印刷电路板接触垫。 还公开了制造该装置的方法。

公开(公告)号：US08242593B2

公开(公告)日：2012-08-14

申请号：US12020565

申请日：2008-01-27

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H01L23/04 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09609 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4919 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A substrate via structure for stacked vias in a substrate/chip assembly includes: a center via stack and a plurality of stacked vias clustered around the center via stack. In this structure, the center via and the surrounding vias are made of copper. Some of the surrounding vias may be non-functional vias and these may be of a different height than the functional vias.

Abstract translation: 用于衬底/芯片组件中的堆叠通孔的衬底通孔结构包括：中心通孔堆叠和多个堆叠的通孔，围绕中心通过堆叠聚集。 在这种结构中，中心通孔和周围的通孔由铜制成。 一些周围的通孔可以是非功能通孔，并且它们可以具有与功能通孔不同的高度。

公开(公告)号：US20120192418A1

公开(公告)日：2012-08-02

申请号：US13435977

申请日：2012-03-30

Applicant: Karan Kacker ,  Suresh K. Sitaraman

Inventor： Karan Kacker ,  Suresh K. Sitaraman

IPC: H01R43/16

CPC classification number: H01R13/2407 ,  H01L23/49811 ,  H01L2924/0002 ,  H05K3/4092 ,  Y10T29/49204 ,  H01L2924/00

Abstract: Disclosed are apparatus comprising single-path and multiple-path compliant interconnects that are coupled between electrical contacts and that allow for increased electrical performance without compromising mechanical reliability. Exemplary apparatus comprises a conductive vertical anchor coupled at a first end to an electrical contact; and one or more conductive arcuate beams coupled at a first end to a second end of the vertical anchor, and coupled at a second end to a second electrical contact. One electrical contact comprises a die contact pad and the other electrical contact comprises a substrate contact pad. Alternatively, one electrical contact comprises a substrate contact pad and the other electrical contact comprises a printed circuit board contact pad. Also, one electrical contact comprises a die contact pad and the other electrical contact comprises a printed circuit board contact pad. Methods of fabricating the apparatus are also disclosed.

Abstract translation: 公开了包括耦合在电触点之间并且允许增加的电性能而不损害机械可靠性的单路径和多路径兼容互连的装置。 示例性设备包括在第一端处耦合到电触点的导电垂直锚固件; 以及一个或多个导电弓形梁，其在第一端处耦合到垂直锚的第二端，并且在第二端处耦合到第二电触点。 一个电触点包括裸片接触焊盘，另一个电触点包括基板接触焊盘。 或者，一个电触点包括基板接触焊盘，另一个电触头包括印刷电路板接触垫。 而且，一个电触头包括裸片接触焊盘，另一个电触点包括印刷电路板接触垫。 还公开了制造该装置的方法。

公开(公告)号：US08522430B2

公开(公告)日：2013-09-03

申请号：US13549440

申请日：2012-07-14

Applicant: Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

Inventor： Karan Kacker ,  Douglas O. Powell ,  David L. Questad ,  David J. Russell ,  Sri M. Sri-Jayantha

IPC: H05K3/40 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L23/498 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05572 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/10253 ,  H01L2924/15151 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09609 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/4919 ,  Y10T29/49204 ,  Y10T29/49222 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A method of fabricating a substrate via structure in a substrate/chip assembly includes steps of: disposing a center via stack for electrical interconnects in the substrate/chip assembly; and providing a plurality of stacked vias surrounding the center via stack. The plurality of stacked vias encircle the center via stack, resulting in no isolated via stacks on the structure. The plurality of stacked vias have both functional and non-functional vias.

Abstract translation: 在衬底/芯片组件中制造衬底通孔结构的方法包括以下步骤：在衬底/芯片组件中布置用于电互连的中心通孔叠层; 以及通过堆叠提供围绕中心的多个堆叠的通孔。 多个堆叠的通孔通过堆叠环绕中心，导致结构上没有隔离的通孔堆叠。 多个堆叠的通孔具有功能和非功能通孔。