发明授权
US08780642B2 Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
有权
分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
- 专利标题： Split gate NAND flash memory structure and array, method of programming, erasing and reading thereof, and method of manufacturing
- 专利标题（中）： 分闸门NAND闪存结构和阵列，编程方法，擦除和读取方法以及制造方法
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申请号： US12872351申请日： 2010-08-31
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公开(公告)号： US08780642B2公开(公告)日： 2014-07-15
- 发明人: Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
- 申请人： Yuniarto Widjaja , John W. Cooksey , Changyuan Chen , Feng Gao , Ya-Fen Lin , Dana Lee
- 申请人地址： US CA San Jose
- 专利权人： Silicon Storage Technology, Inc.
- 当前专利权人： Silicon Storage Technology, Inc.
- 当前专利权人地址： US CA San Jose
- 代理机构： DLA Piper LLP (US)
- 主分类号： G11C11/34
- IPC分类号： G11C11/34 ; G11C16/04
摘要：
A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.
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