发明授权
- 专利标题: Delay locked loop
- 专利标题(中): 延迟锁定环路
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申请号: US13295885申请日: 2011-11-14
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公开(公告)号: US08786338B2公开(公告)日: 2014-07-22
- 发明人: Vijay B. Rentala , Srinath M. Ramaswamy , Brian P. Ginsburg , Eunyoung Seok , Baher S. Haroun
- 申请人: Vijay B. Rentala , Srinath M. Ramaswamy , Brian P. Ginsburg , Eunyoung Seok , Baher S. Haroun
- 申请人地址: US TX Dallas
- 专利权人: Texas Instruments Incorporated
- 当前专利权人: Texas Instruments Incorporated
- 当前专利权人地址: US TX Dallas
- 代理商 John R. Pessetto; Frederick J. Telecky, Jr.
- 主分类号: H03L7/06
- IPC分类号: H03L7/06 ; G01S13/08 ; H03L7/081 ; G01S13/00 ; H03L7/089
摘要:
A method for providing a plurality of narrow pulses is provided. A first pulse having a first width is received by a delay line having a plurality of delay cells. This first pulse has a first width. In response to this first pulse, a plurality of second pulses is generated by the delay line, where each second pulse has a second width that is less than the first width. First and second delay pulses are also generated by the delay line, and a delay for each delay cell in the delay line can then be adjusted if a rising edge of the second delay pulse is misaligned with a falling edge of the first delay pulse.
公开/授权文献
- US20130120186A1 DELAY LOCKED LOOP 公开/授权日:2013-05-16
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