A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.