公开(公告)号：US09306621B2

公开(公告)日：2016-04-05

申请号：US14498383

申请日：2014-09-26

申请人： Broadcom Corporation

发明人： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC分类号： H04B1/74 ,  H03D3/02 ,  H03D3/00 ,  H04L7/033

CPC分类号： H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

摘要翻译： 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US09197214B2

公开(公告)日：2015-11-24

申请号：US14025058

申请日：2013-09-12

申请人： Broadcom Corporation

发明人： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC分类号： H03K19/0175 ,  H03K19/0185

CPC分类号： H03K19/018507

摘要： A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

摘要翻译： 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US20150304098A1

公开(公告)日：2015-10-22

申请号：US14755127

申请日：2015-06-30

申请人： Broadcom Corporation

发明人： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J (Nick) Huang ,  Delong Cui ,  Afshin Momtaz

IPC分类号： H04L7/00

CPC分类号： H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

摘要： A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

摘要翻译： 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US08964907B2

公开(公告)日：2015-02-24

申请号：US13871831

申请日：2013-04-26

申请人： Broadcom Corporation

发明人： Vivek Pundlik Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC分类号： H03D1/00 ,  H04L27/06 ,  H04L27/00 ,  H04B1/00

CPC分类号： H04L27/0002 ,  H04B1/0007 ,  H04B1/406

摘要： According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

摘要翻译： 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。

公开(公告)号：US08902094B1

公开(公告)日：2014-12-02

申请号：US14087457

申请日：2013-11-22

申请人： Broadcom Corporation

发明人： Heng Zhang ,  Delong Cui ,  Jun Cao

IPC分类号： H03M1/00 ,  H03M1/08 ,  H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H04L7/00 ,  H03K5/135 ,  H03L7/089

CPC分类号： H03M1/08 ,  H03K5/135 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H04L7/0008

摘要： A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

摘要翻译： 第一时钟发生器接收输入时钟，产生用于时间交织的模数转换器的多电平跟踪和保持电路的第一电平的第一时钟信号，并产生第一时钟信号的时间领先的版本。 多个第二时钟发生器接收输入时钟并产生对应的多个第二时钟信号，以在多电平跟踪和保持电路的第二电平中使用。 多个第二电平时钟发生器包括可调节的延迟，其延迟多个第二时钟信号中的相应一个第二时钟信号的延迟量，该延迟量基于延迟控制信号确定。 反馈控制器基于第一时钟信号的时间引导版本并且还基于多个第二时钟信号中的相应一个产生延迟控制信号。

公开(公告)号：US20130318256A1

公开(公告)日：2013-11-28

申请号：US13875068

申请日：2013-05-01

申请人： Broadcom Corporation

发明人： Brandon Carl Smith ,  Jun Cao

IPC分类号： H04L12/741

CPC分类号： H04L45/745 ,  H04L45/00 ,  H04L45/742 ,  H04L69/12 ,  H04L69/22

摘要： A network device for processing data on a data network includes a port interface configured to receive a data packet from a data network and to send a processed data packet to an egress port of the plurality of ports, a packet evaluation module configured to parse the received data packet and modify the received data packet to form the processed data packet and a search engine configured to perform searches of lookup tables using parsed data packet values and to return search results to the packet evaluation module to assist in modifying the received data packet. At least one lookup table shares at least two different types of entries in that same at least one lookup table, where the search engine is configured to distinguish between the at least two different types of entries in that same at least one lookup table.

摘要翻译： 一种用于在数据网络上处理数据的网络设备包括：端口接口，被配置为从数据网络接收数据分组，并且将经处理的数据分组发送到所述多个端口的出口端口;分组评估模块，被配置为解析所接收的 数据分组，并修改所接收的数据分组以形成经处理的数据分组;以及搜索引擎，其被配置为使用解析的数据分组值执行查找表的搜索，并将搜索结果返回到分组评估模块以帮助修改所接收的数据分组。 至少一个查找表在该相同的至少一个查找表中共享至少两种不同类型的条目，其中搜索引擎被配置为在该相同的至少一个查找表中区分该至少两种不同类型的条目。

公开(公告)号：US09100167B2

公开(公告)日：2015-08-04

申请号：US13691482

申请日：2012-11-30

申请人： Broadcom Corporation

发明人： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

IPC分类号： G06F1/04 ,  H04L7/033 ,  G06F1/10 ,  H04L25/14 ,  H04L7/00

CPC分类号： H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

摘要： A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

摘要翻译： 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

公开(公告)号：US20150084800A1

公开(公告)日：2015-03-26

申请号：US14040467

申请日：2013-09-27

申请人： Broadcom Corporation

发明人： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC分类号： H03M1/12

CPC分类号： H03M1/0624 ,  H03M1/00 ,  H03M1/1215

摘要： Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

摘要翻译： 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US20150010044A1

公开(公告)日：2015-01-08

申请号：US14498383

申请日：2014-09-26

申请人： Broadcom Corporation

发明人： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC分类号： H04B1/74 ,  H04L7/033

CPC分类号： H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

摘要翻译： 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US08928355B2

公开(公告)日：2015-01-06

申请号：US13867883

申请日：2013-04-22

申请人： Broadcom Corporation

发明人： Delong Cui ,  Afshin Momtaz ,  Jun Cao

IPC分类号： H03K19/094 ,  H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45

CPC分类号： H03F3/16 ,  H03F1/42 ,  H03F3/195 ,  H03F3/45183 ,  H03F2200/336 ,  H03F2200/423 ,  H03F2203/45631 ,  H03F2203/45638 ,  H03F2203/45702 ,  H03F2203/45706

摘要： There is presented a high bandwidth circuit for high-speed transceivers. The circuit may comprise an amplifier combining capacitor splitting, inductance tree structures, and various bandwidth extension techniques such as shunt peaking, series peaking, and T-coil peaking to support data rates of 45 Gbs/s and above while reducing data jitter. The inductance elements of the inductance tree structures may also comprise high impedance transmission lines, simplifying implementation. Additionally, the readily identifiable metal structures of inductors and t-coils, the equal partitioning of the load capacitors, and the symmetrical inductance tree structures may simplify transceiver implementation for, but not limited to, a clock data recovery circuit.

摘要翻译： 为高速收发器提供了高带宽电路。 该电路可以包括组合电容器分离，电感树结构和各种带宽扩展技术的放大器，例如并联峰值，串联峰值和T形线圈峰值，以支持45Gbs / s及以上的数据速率，同时减少数据抖动。 电感树结构的电感元件还可以包括高阻抗传输线，从而简化了实现。 此外，电感器和t-线圈的容易识别的金属结构，负载电容器的相等分配以及对称的电感树结构可以简化收发器实现，但不限于时钟数据恢复电路。