中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

7 records (took 0.012 seconds)

    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
    1.
    发明申请
    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT 审中-公开
    MULTILANE SERDES时钟和数据轴对齐多标准支持

    公开(公告)号：US20150304098A1

    公开(公告)日：2015-10-22

    申请号：US14755127

    申请日：2015-06-30

    Applicant: Broadcom Corporation

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J (Nick) Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: H04L7/00

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    Multilane SERDES clock and data skew alignment for multi-standard support
    2.
    发明授权
    Multilane SERDES clock and data skew alignment for multi-standard support 有权
    多晶硅SERDES时钟和数据偏移对齐，适用于多标准支持

    公开(公告)号：US09100167B2

    公开(公告)日：2015-08-04

    申请号：US13691482

    申请日：2012-11-30

    Applicant: Broadcom Corporation

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: G06F1/04 ,  H04L7/033 ,  G06F1/10 ,  H04L25/14 ,  H04L7/00

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
    3.
    发明申请
    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT 有权
    MULTILANE SERDES时钟和数据轴对齐多标准支持

    公开(公告)号：US20140153680A1

    公开(公告)日：2014-06-05

    申请号：US13691482

    申请日：2012-11-30

    Applicant: BROADCOM CORPORATION

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: H04L7/033

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    DISTRIBUTED RESONATE CLOCK DRIVER
    4.
    发明申请
    DISTRIBUTED RESONATE CLOCK DRIVER 有权
    分布式共振时钟驱动器

    公开(公告)号：US20140055180A1

    公开(公告)日：2014-02-27

    申请号：US13622223

    申请日：2012-09-18

    Applicant: BROADCOM CORPORATION

    Inventor： Adesh Garg ,  Jun Cao

    IPC: H03K3/02 ,  H03L7/06

    CPC classification number: H03K5/135 ,  G06F1/10

    Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

    Abstract translation: 时钟驱动器包括运行到集成电路芯片的多个通道的时钟互连，该互连包括正时钟线和负时钟线。 时钟发生器产生时钟信号和源电感器，时钟发生器通过该电感器吸取直流电源，有助于将时钟信号驱动到互连。 源电感可以是可调谐的。 分布式（或可调谐）电感器连接到源电感器和互连端之间的正和负时钟线并且位于其间。 多个分布式电感器可以被定位并且可选地调谐，以便在时钟信号中产生具有基本相似的质量和幅度的谐振响应，并且输送到多个通道。 任何分布式和源极感应器都可以切换以改变分布式电感器的电感，从而改变不同通信标准的通道中的时钟频率。

    Low-power high swing CML driver with independent common-mode and swing control
    6.
    发明授权
    Low-power high swing CML driver with independent common-mode and swing control 有权
    低功耗高档CML驱动器，具有独立的共模和摆幅控制

    公开(公告)号：US09325316B1

    公开(公告)日：2016-04-26

    申请号：US14709368

    申请日：2015-05-11

    Applicant: BROADCOM CORPORATION

    Inventor： Amr Amin Hafez Amin Abou-El-Sonoun ,  Ramy Awad ,  Mohammed Abdul-Latif ,  Adesh Garg ,  Henry Park ,  Anand Jitendra Vasani ,  Ullas Singh ,  Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03L5/02 ,  H03K19/0185

    CPC classification number: H03K19/018514

    Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

    Abstract translation: 低功率高频摆动电流模式逻辑（CML）驱动电路包括第一差分对和第二差分对。 第一差分对包括第一晶体管，并且耦合到提供第一电压的第一电压源。 第二差分对包括第二晶体管，并且第二差分对的公共节点耦合到第二电压源。 第二电压源提供高于第一电压的第二电压。 第一晶体管的控制端子耦合到第二晶体管的控制端，以形成驱动器电路的输入节点。

    Distributed resonate clock driver
    7.
    发明授权
    Distributed resonate clock driver 有权
    分布式谐振时钟驱动器

    公开(公告)号：US08791742B2

    公开(公告)日：2014-07-29

    申请号：US13622223

    申请日：2012-09-18

    Applicant: Broadcom Corporation

    Inventor： Adesh Garg ,  Jun Cao

    IPC: G06F1/04

    CPC classification number: H03K5/135 ,  G06F1/10

    Abstract: A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

    Abstract translation: 时钟驱动器包括运行到集成电路芯片的多个通道的时钟互连，该互连包括正时钟线和负时钟线。 时钟发生器产生时钟信号和源电感器，时钟发生器通过该电感器吸取直流电源，有助于将时钟信号驱动到互连。 源电感可以是可调谐的。 分布式（或可调谐）电感器连接到源电感器和互连端之间的正和负时钟线并且位于其间。 多个分布式电感器可以被定位并且可选地调谐，以便在时钟信号中产生具有基本相似的质量和幅度的谐振响应，并且输送到多个通道。 任何分布式和源极感应器都可以切换以改变分布式电感器的电感，从而改变不同通信标准的通道中的时钟频率。

Patent Agency Ranking