Invention Grant
US08795540B2 Selective bias compensation for patterning steps in CMOS processes
有权
CMOS工艺中图案化步骤的选择性偏置补偿
- Patent Title: Selective bias compensation for patterning steps in CMOS processes
- Patent Title (中): CMOS工艺中图案化步骤的选择性偏置补偿
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Application No.: US13335618Application Date: 2011-12-22
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Publication No.: US08795540B2Publication Date: 2014-08-05
- Inventor: Ming-Feng Shieh , Ching-Yu Chang
- Applicant: Ming-Feng Shieh , Ching-Yu Chang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater and Matsil, L.L.P.
- Main IPC: C03C15/00
- IPC: C03C15/00 ; H01L21/033
Abstract:
A method includes forming a photo resist pattern, and performing a light-exposure on a first portion of the photo resist pattern, wherein a second portion of the photo resist pattern is not exposed to light. A photo-acid reactive material is coated on the first portion and the second portion of the photo resist pattern. The photo-acid reactive material reacts with the photo resist pattern to form a film. Portions of the photo-acid reactive material that do not react with the photo resist pattern are then removed, and the film is left on the photo resist pattern.
Public/Granted literature
- US20130164938A1 Selective Bias Compensation for Patterning Steps in CMOS Processes Public/Granted day:2013-06-27
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