Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate

Invention Grant

US08796086B2 Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate 有权

Title translation: 形成存储单元阵列的方法，形成多个场效应晶体管的方法，形成源极/漏极区域和隔离沟槽的方法以及将一系列间隔开的沟槽形成衬底的方法

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Patent Title: Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate
Patent Title (中): 形成存储单元阵列的方法，形成多个场效应晶体管的方法，形成源极/漏极区域和隔离沟槽的方法以及将一系列间隔开的沟槽形成衬底的方法
Application No.: US14053665

Application Date: 2013-10-15
Publication No.: US08796086B2

Publication Date: 2014-08-05
Inventor: Neal L. Davis , Richard T. Housley , Ranjan Khurana
Applicant: Micron Technology, Inc.
Applicant Address: US ID Boise
Assignee: Micron Technology, Inc.
Current Assignee: Micron Technology, Inc.
Current Assignee Address: US ID Boise
Agency: Wells St. John, P.S.
Main IPC: H01L21/8238
IPC: H01L21/8238

Methods of forming an array of memory cells, methods of forming a plurality of field effect transistors, methods of forming source/drain regions and isolation trenches, and methods of forming a series of spaced trenches into a substrate

Abstract:

A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

Abstract(Chinese):

将一系列间隔开的沟槽形成到衬底中的方法包括在衬底上形成多个间隔开的线。各向异性蚀刻的侧壁间隔物形成在间隔开的线的相对侧上。这些线的个体具有比在紧邻线之间的紧邻的间隔物之间的最小宽度的最大宽度。去除间隔的线以在间隔件之间形成一系列交替的第一和第二掩模开口。第一掩模开口位于间隔开的线的位置并且比第二掩模开口更宽。交替的第一和第二沟槽分别通过交替的第一和第二掩模开口同时蚀刻到衬底中，以形成比第二沟槽在衬底内更宽和更深的第一沟槽。公开了其他实现和实施例。

Public/Granted literature

US20140045317A1 Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate Public/Granted day:2014-02-13

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS