利索-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.017 seconds)

    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate
    1.
    发明申请
    Methods Of Forming An Array Of Memory Cells, Methods Of Forming A Plurality Of Field Effect Transistors, Methods Of Forming Source/Drain Regions And Isolation Trenches, And Methods Of Forming A Series Of Spaced Trenches Into A Substrate 有权
    形成记忆体阵列的方法，形成多个场效应晶体管的方法，形成源极/漏极区域的方法和隔离沟槽以及将一系列间距沟槽形成基板的方法

    公开(公告)号：US20140045317A1

    公开(公告)日：2014-02-13

    申请号：US14053665

    申请日：2013-10-15

    Applicant: Micron Technology, Inc.

    Inventor： Neal L. Davis ,  Richard T. Housley ,  Ranjan Khurana

    IPC: H01L21/762

    CPC classification number: H01L21/76224 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052

    Abstract: A method of forming a series of spaced trenches into a substrate includes forming a plurality of spaced lines over a substrate. Anisotropically etched sidewall spacers are formed on opposing sides of the spaced lines. Individual of the lines have greater maximum width than minimum width of space between immediately adjacent of the spacers between immediately adjacent of the lines. The spaced lines are removed to form a series of alternating first and second mask openings between the spacers. The first mask openings are located where the spaced lines were located and are wider than the second mask openings. Alternating first and second trenches are simultaneously etched into the substrate through the alternating first and second mask openings, respectively, to form the first trenches to be wider and deeper within the substrate than are the second trenches. Other implementations and embodiments are disclosed.

    Abstract translation: 将一系列间隔开的沟槽形成到衬底中的方法包括在衬底上形成多个间隔开的线。 各向异性蚀刻的侧壁间隔物形成在间隔开的线的相对侧上。 这些线的个体具有比在紧邻线之间的紧邻的间隔物之间​​的最小宽度的最大宽度。 去除间隔的线以在间隔件之间形成一系列交替的第一和第二掩模开口。 第一掩模开口位于间隔开的线的位置并且比第二掩模开口更宽。 交替的第一和第二沟槽分别通过交替的第一和第二掩模开口同时蚀刻到衬底中，以形成比第二沟槽在衬底内更宽和更深的第一沟槽。 公开了其他实现和实施例。

    Methods of forming semiconductor device structures, and related semiconductor device structures
    2.
    发明授权
    Methods of forming semiconductor device structures, and related semiconductor device structures 有权
    形成半导体器件结构的方法以及相关的半导体器件结构

    公开(公告)号：US09229328B2

    公开(公告)日：2016-01-05

    申请号：US13875918

    申请日：2013-05-02

    Applicant: Micron Technology, Inc.

    Inventor： Ranjan Khurana ,  Gurpreet S. Lugani ,  Dan B. Millward

    IPC: G03F7/40

    CPC classification number: G03F7/40 ,  G03F7/0002

    Abstract: A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential wetting to a polymer block of a block copolymer. A positive tone photoresist material is formed over the template material. The positive tone photoresist material is exposed to radiation to form photoexposed regions and non-photoexposed regions of the positive tone photoresist material. The non-photoexposed regions of the positive tone photoresist material are removed with a negative tone developer to form a pattern of photoresist features. The pattern of photoresist features and unprotected portions of the template material are exposed to an oxidizing plasma to form trimmed photoresist features and a pattern of template features. The trimmed photoresist features are removed with a positive tone developer. Other methods of forming a semiconductor device structure, and a semiconductor device structure are also described.

    Abstract translation: 形成半导体器件结构的方法包括在衬底上形成模板材料，该模板材料对嵌段共聚物的聚合物嵌段表现优先润湿。 在模板材料上形成正色调光致抗蚀剂材料。 正色光致抗蚀剂材料暴露于辐射以形成正色调光致抗蚀剂材料的光引射区域和非光照区域。 用负色调显影剂除去正色调光致抗蚀剂材料的非光引射区域以形成光刻胶特征图案。 模板材料的光致抗蚀剂特征图案和未保护部分的图案暴露于氧化等离子体以形成修整的光致抗蚀剂特征和模板特征图案。 用正色调显影剂除去修剪的光致抗蚀剂特征。 还描述了形成半导体器件结构的其它方法以及半导体器件结构。

    Methods of Forming A Pattern On A Substrate
    3.
    发明申请
    Methods of Forming A Pattern On A Substrate 有权
    在基板上形成图案的方法

    公开(公告)号：US20140162459A1

    公开(公告)日：2014-06-12

    申请号：US13712830

    申请日：2012-12-12

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Shane J. Trapp ,  Ranjan Khurana ,  Kevin R. Shea

    IPC: H01L21/308

    CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/266 ,  H01L21/31144 ,  H01L21/76816 ,  Y10S438/947

    Abstract: A method of forming a pattern on a substrate includes forming spaced first material-comprising pillars projecting elevationally outward of first openings formed in second material. Sidewall spacers are formed over sidewalls of the first material-comprising pillars. The sidewall spacers form interstitial spaces laterally outward of the first material-comprising pillars. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall spacers that are over sidewalls of four of the first material-comprising pillars.

    Abstract translation: 在衬底上形成图案的方法包括在第二材料中形成的第一开口的高度向外突出形成间隔开的第一材料包括柱。 在第一含材料柱的侧壁上形成侧壁间隔物。 侧壁间隔物在第一含材料柱的横向向外形成间隙空间。 间隙空间由四个第一材料包括柱的侧壁上的纵向接触的侧壁间隔单独包围。

    METHODS FOR FORMING SUB-RESOLUTION FEATURES IN SEMICONDUCTOR DEVICES
    6.
    发明申请
    METHODS FOR FORMING SUB-RESOLUTION FEATURES IN SEMICONDUCTOR DEVICES 有权
    在半导体器件中形成分解特征的方法

    公开(公告)号：US20140370684A1

    公开(公告)日：2014-12-18

    申请号：US13918065

    申请日：2013-06-14

    Applicant: Micron Technology, Inc.

    Inventor： Ranjan Khurana ,  Michael Hyatt ,  Scott L. Light ,  Kevin J. Torek ,  Anton J. deVilliers

    IPC: H01L21/768 ,  H01L49/02

    CPC classification number: H01L21/76816 ,  G03F7/0035 ,  G03F7/095 ,  H01L21/0273 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L28/90

    Abstract: Methods of forming semiconductor devices and features in semiconductor device structures include conducting an anti-spacer process to remove portions of a first mask material to form first openings extending in a first direction. Another anti-spacer process is conducted to remove portions of the first mask material to form second openings extending in a second direction at an angle to the first direction. Portions of the second mask material underlying the first mask material at intersections of the first openings and second openings are removed to form holes in the second mask material and to expose a substrate underlying the second mask material.

    Abstract translation: 在半导体器件结构中形成半导体器件和特征的方法包括进行防间隔工艺以去除第一掩模材料的部分以形成沿第一方向延伸的第一开口。 进行另一个防间隔处理以去除第一掩模材料的部分，以形成沿与第一方向成角度的第二方向延伸的第二开口。 去除在第一开口和第二开口的交叉点处的第一掩模材料下面的第二掩模材料的部分，以在第二掩模材料中形成孔并暴露第二掩模材料下面的衬底。

    Semiconductor constructions and methods of forming semiconductor constructions
    9.
    发明授权
    Semiconductor constructions and methods of forming semiconductor constructions 有权
    半导体结构和形成半导体结构的方法

    公开(公告)号：US09460998B2

    公开(公告)日：2016-10-04

    申请号：US14259313

    申请日：2014-04-23

    Applicant: Micron Technology, Inc.

    Inventor： Justin B. Dorhout ,  Ranjan Khurana ,  David Swindler ,  Jianming Zhou

    IPC: H01L23/52 ,  H01L23/528 ,  H01L21/033 ,  H01L21/311 ,  H01L21/768

    CPC classification number: H01L23/528 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/76816 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

    Abstract translation: 一些实施例包括具有主要沿着第一方向延伸的一对线并且在线之间具有一对接触的半导体结构。 触点通过光刻尺寸彼此间隔开，并且通过亚光刻尺寸与线间隔开。 一些实施例包括形成半导体结构的方法。 特征形成在一个基地上。 每个特征具有第一类型侧壁和第二类型侧壁。 这些特征通过间隙彼此间隔开。 一些间隙是第一类型侧壁之间的第一类型间隙，而其它间隙是第二类型侧壁之间的第二类型间隙。 形成掩模材料以相对于第二类型间隙选择性地填充第一类型的间隙。 去除过量的掩模材料以留下图案化掩模。 图案从图案化掩模转移到基底中。

    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES
    10.
    发明申请
    METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES, AND RELATED SEMICONDUCTOR DEVICE STRUCTURES 有权
    形成半导体器件结构的方法和相关半导体器件结构

    公开(公告)号：US20140329179A1

    公开(公告)日：2014-11-06

    申请号：US13875918

    申请日：2013-05-02

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Ranjan Khurana ,  Gurpreet S. Lugani ,  Dan B. Millward

    IPC: G03F7/40

    CPC classification number: G03F7/40 ,  G03F7/0002

    Abstract: A method of forming a semiconductor device structure comprises forming a template material over a substrate, the template material exhibiting preferential wetting to a polymer block of a block copolymer. A positive tone photoresist material is formed over the template material. The positive tone photoresist material is exposed to radiation to form photoexposed regions and non-photoexposed regions of the positive tone photoresist material. The non-photoexposed regions of the positive tone photoresist material are removed with a negative tone developer to form a pattern of photoresist features. The pattern of photoresist features and unprotected portions of the template material are exposed to an oxidizing plasma to form trimmed photoresist features and a pattern of template features. The trimmed photoresist features are removed with a positive tone developer. Other methods of forming a semiconductor device structure, and a semiconductor device structure are also described.

    Abstract translation: 形成半导体器件结构的方法包括在衬底上形成模板材料，该模板材料对嵌段共聚物的聚合物嵌段表现优先润湿。 在模板材料上形成正色调光致抗蚀剂材料。 正色光致抗蚀剂材料暴露于辐射以形成正色调光致抗蚀剂材料的光引射区域和非光照区域。 用负色调显影剂除去正色调光致抗蚀剂材料的非光引射区域以形成光刻胶特征图案。 模板材料的光致抗蚀剂特征图案和未保护部分的图案暴露于氧化等离子体以形成修整的光致抗蚀剂特征和模板特征图案。 用正色调显影剂除去修剪的光致抗蚀剂特征。 还描述了形成半导体器件结构的其它方法以及半导体器件结构。

Patent Agency Ranking