发明授权
- 专利标题: Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supply
- 专利标题(中): 节能和节能的方法,装置和系统,包括通过使用寄存器二次不间断电源提高处理器核心深度掉电退出延迟
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申请号: US13335880申请日: 2011-12-22
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公开(公告)号: US08819461B2公开(公告)日: 2014-08-26
- 发明人: Inder M. Sodhi , Alon Naveh , Michael Zelikson , Sanjeev s. Jahagirdar , Varghese George
- 申请人: Inder M. Sodhi , Alon Naveh , Michael Zelikson , Sanjeev s. Jahagirdar , Varghese George
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Blakely, Sokoloff, Taylor & Zafman LLP
- 主分类号: G06F1/00
- IPC分类号: G06F1/00
摘要:
Embodiments of the invention relate to improving exit latency from computing device processor core deep power down. Processor state data may be maintained during deep power down mode by providing a secondary uninterrupted voltage supply to always on keeper circuits that reside within critical state registers of the processor. When these registers receive a control signal indicating that the processor power state is going to be reduced from an active processor power state to a zero processor power state, they write critical state data from the critical state register latches to the keeper circuits that are supplied with the uninterrupted power. Then, when a register receives a control signal indicating that a processor power state of the processor is going to be increased back to an active processor power state, the critical state data stored in the keeper circuits is written back to the critical state register latches.