Invention Grant
US08822265B2 Method for reducing forming voltage in resistive random access memory
有权
降低电阻随机存取存储器中成形电压的方法
- Patent Title: Method for reducing forming voltage in resistive random access memory
- Patent Title (中): 降低电阻随机存取存储器中成形电压的方法
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Application No.: US13673504Application Date: 2012-11-09
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Publication No.: US08822265B2Publication Date: 2014-09-02
- Inventor: Prashant B Phatak , Ronald J. Kuse , Jinhong Tong
- Applicant: Intermolecular Inc.
- Applicant Address: US CA San Jose
- Assignee: Intermolecular, Inc.
- Current Assignee: Intermolecular, Inc.
- Current Assignee Address: US CA San Jose
- Main IPC: H01L21/00
- IPC: H01L21/00
Abstract:
Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.
Public/Granted literature
- US20130089949A1 Method for Reducing Forming Voltage in Resistive Random Access Memory Public/Granted day:2013-04-11
Information query
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