公开(公告)号：US08822265B2

公开(公告)日：2014-09-02

申请号：US13673504

申请日：2012-11-09

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak ,  Ronald J. Kuse ,  Jinhong Tong

IPC: H01L21/00

CPC classification number: H01L45/1616 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1641

Abstract: Methods for producing RRAM resistive switching elements having reduced forming voltage include preventing formation of interfacial layers, and creating electronic defects in a dielectric film. Suppressing interfacial layers in an electrode reduces forming voltage. Electronic defects in a dielectric film foster formation of conductive pathways.

Abstract translation: 制造具有降低的成形电压的RRAM电阻式开关元件的方法包括阻止形成界面层，并在电介质膜中产生电子缺陷。 抑制电极中的界面层降低成形电压。 电介质膜中的电子缺陷促进导电通路的形成。

公开(公告)号：US20150255716A1

公开(公告)日：2015-09-10

申请号：US14721640

申请日：2015-05-26

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak ,  Tony P. Chiang ,  Pragati Kumar ,  Michael Miller

IPC: H01L45/00

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

公开(公告)号：US20150137062A1

公开(公告)日：2015-05-21

申请号：US14560031

申请日：2014-12-04

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B Phatak

IPC: H01L27/24 ,  H01L49/02

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/76 ,  G11C2213/77 ,  H01L21/324 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices suitable for memory arrays have low leakage currents at low voltages, reducing sneak current paths for non-selected devices, and high leakage currents at high voltages, reducing voltage drops during switching. The selector device may include a non-conductive tri-layer between two electrodes. The non-conductive tri-layer may include a low-bandgap dielectric layer between two higher-bandgap dielectric layers. The high-bandgap dielectric layers may be doped to form traps at energy levels higher than the write voltage of the memory device. With a thin low-bandgap layer and a large bandgap difference from the high-bandgap layers, the selector may operate as a quantum well, conductive when the electrode Fermi level matches the lowest energy level of the quantum well and insulating at lower voltages.

Abstract translation: 适用于存储器阵列的选择器件在低电压下具有低漏电流，减少非选定器件的潜行电流路径，以及高电压下的高泄漏电流，从而减少开关期间的电压降。 选择器装置可以包括两个电极之间的非导电三层。 非导电三层可以包括两个较高带隙电介质层之间的低带隙电介质层。 可以掺杂高带隙电介质层以在高于存储器件的写入电压的能级形成陷阱。 具有薄的低带隙层和与高带隙层的大带隙差异，当电极费米能级与量子阱的最低能级匹配并在较低电压下绝缘时，选择器可以作为量子阱进行导电。

公开(公告)号：US08963117B2

公开(公告)日：2015-02-24

申请号：US14018719

申请日：2013-09-05

Applicant: Intermolecular Inc.

Inventor： Pragati Kumar ,  Tony P. Chiang ,  Prashant B Phatak ,  Yun Wang

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0002 ,  G11C2013/0083 ,  G11C2213/51 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1625 ,  H01L45/1641

Abstract: This disclosure provides a nonvolatile memory device and related methods of manufacture and operation. The device may include one or more resistive random access memory (ReRAM) approaches to provide a memory device with more predictable operation. In particular, the forming voltage required by particular designs may be reduced through the use of a barrier layer, a reverse polarity forming voltage pulse, a forming voltage pulse where electrons are injected from a lower work function electrode, or an anneal in a reducing environment. One or more of these techniques may be applied, depending on the desired application and results.

公开(公告)号：US09178149B2

公开(公告)日：2015-11-03

申请号：US14325015

申请日：2014-07-07

Applicant: Intermolecular Inc.

Inventor： Michael Miller ,  Tony P. Chiang ,  Xiying Costa ,  Tanmay Kumar ,  Prashant B Phatak ,  April Schricker

IPC: H01L21/20 ,  H01L45/00 ,  H01L21/265 ,  H01L21/3115 ,  H01L29/861 ,  H01L27/24

CPC classification number: H01L45/16 ,  H01L21/265 ,  H01L21/31155 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165

Abstract: This disclosure provides a method of fabricating a semiconductor device layer and associated memory cell structures. By performing a surface treatment process (such as ion bombardment) of a semiconductor device layer to create defects having a deliberate depth profile, one may create multistable memory cells having more consistent electrical parameters. For example, in a resistive-switching memory cell, one may obtain a tighter distribution of set and reset voltages and lower forming voltage, leading to improved device yield and reliability. In at least one embodiment, the depth profile is selected to modulate the type of defects and their influence on electrical properties of a bombarded metal oxide layer and to enhance uniform defect distribution.

Abstract translation: 本公开提供了制造半导体器件层和相关联的存储单元结构的方法。 通过进行半导体器件层的表面处理（例如离子轰击）以产生具有有意深度分布的缺陷，可以创建具有更一致的电参数的多层存储单元。 例如，在电阻式开关存储单元中，可以获得设定和复位电压的更紧密的分配和较低的成形电压，从而提高器件的产量和可靠性。 在至少一个实施例中，选择深度轮廓以调制缺陷的类型及其对被轰击的金属氧化物层的电性能的影响并增强均匀的缺陷分布。

公开(公告)号：US09070867B2

公开(公告)日：2015-06-30

申请号：US14549680

申请日：2014-11-21

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak ,  Tony P. Chiang ,  Pragati Kumar ,  Michael Miller

IPC: H01L45/00 ,  H01L47/00 ,  H01L29/861 ,  G11C13/00 ,  H01L27/24

CPC classification number: H01L45/146 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/55 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L29/8615 ,  H01L45/08 ,  H01L45/10 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1616 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/165 ,  H01L45/1658 ,  H01L47/00

Abstract: Non-volatile resistive-switching memories are described, including a memory element having a first electrode, a second electrode, a metal oxide between the first electrode and the second electrode. The metal oxide switches using bulk-mediated switching, has a bandgap greater than 4 electron volts (eV), has a set voltage for a set operation of at least one volt per one hundred angstroms of a thickness of the metal oxide, and has a leakage current density less than 40 amps per square centimeter (A/cm2) measured at 0.5 volts (V) per twenty angstroms of the thickness of the metal oxide.

Abstract translation: 描述了非易失性电阻式切换存储器，包括在第一电极和第二电极之间具有第一电极，第二电极，金属氧化物的存储元件。 使用大容量介导的开关的金属氧化物开关具有大于4电子伏特（eV）的带隙，具有用于金属氧化物的厚度每100埃至少一伏特的设定操作的设定电压，并且具有 漏电流密度小于每平方厘米40安培（A / cm2），每0.5伏（V），金属氧化物厚度每20埃测得。

公开(公告)号：US09029187B1

公开(公告)日：2015-05-12

申请号：US14559886

申请日：2014-12-03

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B Phatak

IPC: H01L21/00 ,  H01L27/24 ,  H01L49/02 ,  H01L21/02 ,  H01L21/324 ,  H01L21/283

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件切换期间的电压降。 选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括设置在两个较高带隙电介质层之间的低带隙电介质层。 高带隙电介质层可以掺杂掺杂材料以在高于存储器件的工作电压的能级下形成阱。

公开(公告)号：US08976565B2

公开(公告)日：2015-03-10

申请号：US13693820

申请日：2012-12-04

Applicant: Intermolecular Inc.

Inventor： Prashant B Phatak

IPC: G11C11/36 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L28/60 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02186 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/0228 ,  H01L21/02323 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/32055 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/00 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: MIMCAP diodes are provided that can be suitable for memory device applications, such as current selector devices for cross point memory array. The MIMCAP diodes can have lower thermal budget as compared to Schottky diodes and controllable lower barrier height and lower series resistance as compared to MIMCAP tunneling diodes. The MIMCAP diode can include a barrier height modification layer, a low leakage dielectric layer and a high leakage dielectric layer. The layers can be sandwiched between two electrodes.

Abstract translation: 提供了可适用于存储器件应用的MIMCAP二极管，例如用于交叉点存储器阵列的电流选择器装置。 与MIMCAP隧道二极管相比，MIMCAP二极管可以具有比肖特基二极管更低的热预算和可控的较低势垒高度和较低的串联电阻。 MIMCAP二极管可以包括阻挡层高度改性层，低漏电介质层和高泄漏电介质层。 这些层可以夹在两个电极之间。

公开(公告)号：US09029232B2

公开(公告)日：2015-05-12

申请号：US14281550

申请日：2014-05-19

Applicant: Intermolecular Inc.

Inventor： Sandra G Malhotra ,  Sean Barstow ,  Tony P. Chiang ,  Wayne R French ,  Pragati Kumar ,  Prashant B Phatak ,  Sunil Shanker ,  Wen Wu

IPC: H01L21/02 ,  H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1608 ,  H01L27/2418 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641

Abstract: Nonvolatile memory elements that are based on resistive switching memory element layers are provided. A nonvolatile memory element may have a resistive switching metal oxide layer. The resistive switching metal oxide layer may have one or more layers of oxide. A resistive switching metal oxide may be doped with a dopant that increases its melting temperature and enhances its thermal stability. Layers may be formed to enhance the thermal stability of the nonvolatile memory element. An electrode for a nonvolatile memory element may contain a conductive layer and a buffer layer.

Abstract translation: 提供了基于电阻式开关存储元件层的非易失性存储元件。 非易失性存储元件可以具有电阻性开关金属氧化物层。 电阻式开关金属氧化物层可以具有一层或多层氧化物。 电阻式开关金属氧化物可以掺杂有增加其熔融温度并增强其热稳定性的掺杂剂。 可以形成层以增强非易失性存储元件的热稳定性。 用于非易失性存储元件的电极可以包含导电层和缓冲层。

公开(公告)号：US08933429B2

公开(公告)日：2015-01-13

申请号：US13974278

申请日：2013-08-23

Applicant: Intermolecular Inc.

Inventor： Venkat Ananthan ,  Prashant B Phatak

IPC: H01L47/00 ,  H01L45/00 ,  G11C13/00 ,  H01L21/66

CPC classification number: H01L27/2418 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  G11C2213/15 ,  G11C2213/71 ,  G11C2213/77 ,  H01L21/02183 ,  H01L21/02186 ,  H01L21/0228 ,  H01L21/0234 ,  H01L21/283 ,  H01L21/324 ,  H01L22/12 ,  H01L22/34 ,  H01L27/24 ,  H01L27/2463 ,  H01L28/60 ,  H01L45/00 ,  H01L45/04 ,  H01L45/08 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/1266 ,  H01L45/14 ,  H01L45/144 ,  H01L45/145 ,  H01L45/16 ,  H01L45/1608 ,  H01L45/1616 ,  H01L45/1641 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Selector devices that can be suitable for memory device applications can have low leakage currents at low voltages to reduce sneak current paths for non selected devices, and high leakage currents at high voltages to minimize voltage drops during device switching. The selector device can include a first electrode, a tri-layer dielectric layer, and a second electrode. The tri-layer dielectric layer can include a low band gap dielectric layer disposed between two higher band gap dielectric layers. The high band gap dielectric layers can be doped with doping materials to form traps at energy levels higher than the operating voltage of the memory device.

Abstract translation: 可适用于存储器件应用的选择器器件可在低电压下具有低漏电流，以减少非选定器件的漏电流路径，以及高电压下的高泄漏电流，以最大限度地减少器件开关期间的电压降。 选择器装置可以包括第一电极，三层电介质层和第二电极。 三层电介质层可以包括设置在两个较高带隙电介质层之间的低带隙电介质层。 高带隙电介质层可以掺杂掺杂材料以在高于存储器件的工作电压的能级下形成阱。