Invention Grant
US08828851B2 Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
有权
用于形成用于PFET阈值电压工程的FDSOI器件的硅锗通道的方法
- Patent Title: Method to enable the formation of silicon germanium channel of FDSOI devices for PFET threshold voltage engineering
- Patent Title (中): 用于形成用于PFET阈值电压工程的FDSOI器件的硅锗通道的方法
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Application No.: US13487583Application Date: 2012-06-04
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Publication No.: US08828851B2Publication Date: 2014-09-09
- Inventor: Nicolas Loubet , Prasanna Khare , Qing Liu
- Applicant: Nicolas Loubet , Prasanna Khare , Qing Liu
- Applicant Address: US TX Coppell
- Assignee: STMicroeletronics, Inc.
- Current Assignee: STMicroeletronics, Inc.
- Current Assignee Address: US TX Coppell
- Agency: Gardere Wynne Sewell LLP
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L21/20 ; H01L29/78

Abstract:
An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.
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