公开(公告)号：US08828851B2

公开(公告)日：2014-09-09

申请号：US13487583

申请日：2012-06-04

Applicant: Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

Inventor： Nicolas Loubet ,  Prasanna Khare ,  Qing Liu

IPC: H01L21/336 ,  H01L21/20 ,  H01L29/78

CPC classification number: H01L21/84 ,  H01L27/1207 ,  H01L29/66477 ,  H01L29/66628 ,  H01L29/7848

Abstract: An SOI substrate has a first region isolated from a second region. An SiGe layer is deposited on top of the SOI substrate in the second region. The substrate is subjected to a thermal oxidation process which drives in Ge from the SiGe layer to form an SiGeOI structure in the second region and an overlying oxide layer. If the SOI substrate is exposed in the first region, the thermal oxidation process further produces an oxide layer overlying the first region. The oxide layer(s) is(are) removed to expose an Si channel layer in the first region and an SiGe channel layer in the second region. Transistor gate stacks are formed over each of the Si channel layer and SiGe channel layer. Raised source and drain regions are formed from the Si channel layer and SiGe channel layer adjacent the transistor gate stacks.

Abstract translation: SOI衬底具有与第二区域隔离的第一区域。 SiGe层沉积在第二区域中的SOI衬底的顶部上。 对衬底进行热氧化处理，其在GeGe层中驱动Ge，以在第二区域和上覆氧化物层中形成SiGeOI结构。 如果SOI衬底在第一区域中暴露，则热氧化工艺进一步产生覆盖第一区域的氧化物层。 去除氧化物层以暴露第一区域中的Si沟道层和第二区域中的SiGe沟道层。 在每个Si沟道层和SiGe沟道层上形成晶体管栅极叠层。 上升的源极和漏极区域由Si沟道层和与晶体管栅极叠层相邻的SiGe沟道层形成。

公开(公告)号：US07881594B2

公开(公告)日：2011-02-01

申请号：US12005862

申请日：2007-12-27

Applicant: Ming Fang ,  Fuchao Wang

Inventor： Ming Fang ,  Fuchao Wang

IPC: F24H1/10

CPC classification number: B81C1/00119 ,  B41J2/14056 ,  B41J2/14072 ,  B41J2/14137 ,  B41J2/16 ,  B41J2/1601 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1639 ,  B81B1/006 ,  B81B2201/052 ,  B81B2201/058 ,  B81C2201/013 ,  B81C2203/075 ,  H01L28/20 ,  Y10T29/41 ,  Y10T29/49401 ,  Y10T29/49826

Abstract: An integrated semiconductor heating assembly includes a semiconductor substrate, a chamber formed therein, and an exit port in fluid communication with the chamber, allowing fluid to exit the chamber in response to heating the chamber. The integrated heating assembly includes a first heating element adjacent the chamber, which can generate heat above a selected threshold and bias fluid in the chamber toward the exit port. A second heating element is positioned adjacent the exit port to generate heat above a selected threshold, facilitating movement of the fluid through the exit port away from the chamber. Addition of the second heating element reduces the amount of heat emitted per heating element and minimizes thickness of a heat absorption material toward an open end of the exit port. Since such material is expensive, this reduces the manufacturing cost and retail price of the assembly while improving efficiency and longevity thereof.

Abstract translation: 集成半导体加热组件包括半导体衬底，形成在其中的腔室以及与腔室流体连通的出口，允许流体响应于加热室而离开腔室。 集成加热组件包括邻近腔室的第一加热元件，该第一加热元件可以产生高于选定阈值的热量，并将腔室中的流体朝向出口偏压。 第二加热元件邻近出口定位以产生高于所选阈值的热量，便于流体通过出口远离腔室的运动。 添加第二加热元件减少了每个加热元件发出的热量，并使吸热材料的厚度最小化到出口的开口端。 由于这样的材料是昂贵的，所以这降低了组件的制造成本和零售价格，同时提高了其效率和使用寿命。

公开(公告)号：US5936451A

公开(公告)日：1999-08-10

申请号：US897187

申请日：1997-07-21

Applicant: William A. Phillips ,  Mario Paparo ,  Piero Capocelli

Inventor： William A. Phillips ,  Mario Paparo ,  Piero Capocelli

IPC: G05F3/24 ,  H03K5/13

CPC classification number: H03K5/131 ,  H03K5/133 ,  G05F3/242

Abstract: A reduced area delay circuit and method are disclosed. The delay circuit uses a constant current source and a constant current drain to charge and discharge a capacitor and thus control the delay time of the delay circuit. The constant current source and drain can be implemented using current mirrors formed by configuring MOSFET transistors in a common source configuration. The delay circuit method includes the steps of receiving an input signal, delaying the input signal by using a constant current source or drain in combination with a capacitor, and then buffering the voltage on the capacitor using two inverters. A programmable delay circuit is also disclosed by adding additional pairs of current mirrors to the delay circuit and selectively enabling the pairs to adjust the delay time.

Abstract translation: 公开了一种缩小面积延迟电路和方法。 延迟电路使用恒流源和恒流漏极来对电容器进行充电和放电，从而控制延迟电路的延迟时间。 恒流源和漏极可以使用通过在共同的源配置中配置MOSFET晶体管形成的电流镜来实现。 延迟电路方法包括以下步骤：接收输入信号，通过使用恒定电流源或漏极与电容器组合来延迟输入信号，然后使用两个反相器缓冲电容器上的电压。 还公开了可编程延迟电路，通过向延迟电路增加额外的电流镜对，并且选择性地使得对可以调整延迟时间。