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    SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS
    4.
    发明申请
    SHALLOW HEAVILY DOPED SEMICONDUCTOR LAYER BY CYCLIC SELECTIVE EPITAXIAL DEPOSITION PROCESS 有权
    通过循环选择性外延沉积工艺沉积重金属半导体层

    公开(公告)号：US20140024203A1

    公开(公告)日：2014-01-23

    申请号：US13988436

    申请日：2010-11-19

    申请人： Vincent Destefanis ,  Nicolas Loubet

    发明人： Vincent Destefanis ,  Nicolas Loubet

    IPC分类号： H01L21/02

    CPC分类号： H01L21/0226 ,  H01L21/02499 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0262 ,  H01L21/02642

    摘要： The deposition method comprises providing a substrate with a first mono-crystalline zone made of a semiconductor material and a second zone made of an insulating material. During a passivation step, a passivation atmosphere is applied on the substrate so as to cover the first zone with doping impurities. During a deposition step, gaseous silicon and/or germanium precursors are introduced and a doped semiconductor film is formed. The semiconductor film is mono-crystalline over the first zone and has a different texture over the second zone. During an etching step, a chloride gaseous precursor is applied on the substrate so as to remove the semiconductor layer over the second zone.

    摘要翻译： 沉积方法包括提供具有由半导体材料制成的第一单晶区和由绝缘材料制成的第二区的衬底。 在钝化步骤期间，钝化气氛被施加在衬底上，以便用掺杂杂质覆盖第一区域。 在沉积步骤期间，引入气态硅和/或锗前体并形成掺杂半导体膜。 半导体膜在第一区域上是单晶的，并且在第二区域上具有不同的纹理。 在蚀刻步骤期间，将氯化物气体前体施加在衬底上，以便在第二区域上移除半导体层。

    METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS
    5.
    发明申请
    METHOD FOR FORMING SILICON WELLS OF DIFFERENT CRYSTALLOGRAPHIC ORIENTATIONS 有权
    用于形成不同晶体取向方位硅的方法

    公开(公告)号：US20090023275A1

    公开(公告)日：2009-01-22

    申请号：US12175877

    申请日：2008-07-18

    申请人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

    发明人： Nicolas Loubet ,  Didier Dutartre ,  Frederic Boeuf

    IPC分类号： H01L21/20

    CPC分类号： H01L21/02381 ,  H01L21/02433 ,  H01L21/02532 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02639

    摘要： A method for manufacturing silicon wells of various crystallographic orientations in a silicon support, including the steps of: forming a silicon layer having a first orientation on a silicon substrate having a second orientation; forming insulating walls, defining wells extend at least down to the border between the silicon substrate and the silicon layer; performing, in first wells, a chemical vapor etch (CVE) of the silicon layer by means of hydrochloric acid, in an epitaxy reactor, at a temperature ranging between 700° C. and 950° C.; and performing, in the first wells, a vapor-phase epitaxy on the silicon substrate in the presence of a precursor of silicon and hydrochloric acid, at a temperature ranging between 700° C. and 900° C. and up to the upper surface of the silicon layer.

    摘要翻译： 一种用于制造硅载体中各种晶体取向硅阱的方法，包括以下步骤：在具有第二取向的硅衬底上形成具有第一取向的硅层; 形成绝缘壁，限定阱至少向下延伸到硅衬底和硅层之间的边界; 在外延反应器中，在700℃至950℃的温度范围内，通过盐酸在第一个阱中进行硅层的化学气相蚀刻（CVE）。 并且在第一个阱中，在硅和盐酸的前体存在下，在700℃和900℃之间的温度范围内，在硅衬底上进行气相外延，直到上述表面 硅层。

    Method for fabricating microelectronic devices with isolation trenches partially formed under active regions
    6.
    发明授权
    Method for fabricating microelectronic devices with isolation trenches partially formed under active regions 有权
    用于制造具有在有源区域部分形成的隔离沟槽的微电子器件的方法

    公开(公告)号：US09437474B2

    公开(公告)日：2016-09-06

    申请号：US14425891

    申请日：2012-09-05

    申请人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    发明人： Laurent Grenouillet ,  Yannick Le Tiec ,  Nicolas Loubet ,  Maud Vinet ,  Romain Wacquez

    IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/265 ,  H01L21/306

    CPC分类号： H01L21/76283 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/76232 ,  H01L21/84

    摘要： A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

    摘要翻译： 一种在包括第一半导体层，电介质层和第二半导体层的衬底中制造微电子器件的方法，包括以下步骤：通过所述第一半导体层，所述电介质层和所述第一半导体层的厚度的一部分蚀刻沟槽 从而在所述第一半导体层中限定所述微电子器件的一个有源区域，在所述沟槽的一个或多个侧壁中的离子注入，在所述第二半导体层的水平处，修改所述晶体学性质和/或所述第二半导体层， 注入半导体的化学性质，蚀刻注入的半导体，使得沟槽的至少一部分在有源区的一部分下方延伸，用电介质材料填充沟槽，形成围绕有源区的隔离沟槽，并且包括 在有源区域的一部分下延伸的部分。

    Dual shallow trench isolation liner for preventing electrical shorts
    7.
    发明授权
    Dual shallow trench isolation liner for preventing electrical shorts 有权
    双浅沟槽隔离衬垫，用于防止电气短路

    公开(公告)号：US08703550B2

    公开(公告)日：2014-04-22

    申请号：US13525642

    申请日：2012-06-18

    申请人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    发明人： Bruce B. Doris ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Nicolas Loubet ,  Maud Vinet

    IPC分类号： H01L21/00 ,  H01L21/84

    CPC分类号： H01L21/76879 ,  H01L21/0217 ,  H01L21/76224 ,  H01L21/76283 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76897 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66568 ,  H01L29/66628 ,  H01L29/78609

    摘要： A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

    摘要翻译： 形成浅沟槽以延伸到绝缘体上半导体（SOI）层的处理衬底中。 在浅沟槽中形成介质金属氧化物层和氮化硅层的电介质衬垫层，随后沉积浅沟槽隔离填充部分。 介电衬垫堆叠从顶部半导体部分的顶表面上方移除，随后除去介电金属氧化物层的氮化硅衬垫层和上部垂直部分。 横向围绕顶部半导体部分和掩埋绝缘体部分的堆叠的边角填充有氮化硅部分。 随后形成栅极结构和源极/漏极结构。 氮化硅部分或电介质金属氧化物层在形成源极/漏极接触通孔期间用作停止层，从而防止源极/漏极接触通孔结构和处理衬底之间的电短路。

    TRANSISTOR HAVING A STRESSED BODY
    9.
    发明申请
    TRANSISTOR HAVING A STRESSED BODY 审中-公开
    具有受压身体的晶体管

    公开(公告)号：US20130277747A1

    公开(公告)日：2013-10-24

    申请号：US13454570

    申请日：2012-04-24

    申请人： Qing LIU ,  Nicolas LOUBET ,  Prasanna KHARE

    发明人： Qing LIU ,  Nicolas LOUBET ,  Prasanna KHARE

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

    摘要： An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

    摘要翻译： 晶体管的实施例包括主体和被配置为对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS
    10.
    发明申请
    PROCESS FOR FORMING AN EPITAXIAL LAYER, IN PARTICULAR ON THE SOURCE AND DRAIN REGIONS OF FULLY-DEPLETED TRANSISTORS 审中-公开
    形成外延层的方法，特别是完全放电的晶体管的源和漏区

    公开(公告)号：US20120252174A1

    公开(公告)日：2012-10-04

    申请号：US13434923

    申请日：2012-03-30

    申请人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    发明人： Didier Dutartre ,  Nicolas Loubet ,  Yves Campidelli ,  Denis Pellissier-Tanon

    IPC分类号： H01L21/336 ,  H01L21/20

    CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

    摘要： A layer of a semiconductor material is epitaxially grown on a single-crystal semiconductor structure and on a polycrystalline semiconductor structure. The epitaxial layer is then etched in order to preserve a non-zero thickness of said material on the single-crystal structure and a zero thickness on the polycrystalline structure. The process of growth and etch is repeated, with the same material or with a different material in each repetition, until a stack of epitaxial layers on said single-crystal structure has reached a desired thickness. The single crystal structure is preferably a source/drain region of a transistor, and the polycrystalline structure is preferably a gate of that transistor.

    摘要翻译： 在单晶半导体结构和多晶半导体结构上外延生长半导体材料层。 然后蚀刻外延层，以便在单晶结构上保留所述材料的非零厚度，并在多晶结构上保持零厚度。 在每个重复中，使用相同的材​​料或不同的材料重复生长和蚀刻的过程，直到所述单晶结构上的一叠外延层已经达到期望的厚度。 单晶结构优选为晶体管的源/漏区，多晶结构优选为该晶体管的栅极。