Invention Grant
US08835220B2 Backside mold process for ultra thin substrate and package on package assembly
有权
用于超薄基板和封装组件上的封装的背面模具工艺
- Patent Title: Backside mold process for ultra thin substrate and package on package assembly
- Patent Title (中): 用于超薄基板和封装组件上的封装的背面模具工艺
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Application No.: US13776189Application Date: 2013-02-25
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Publication No.: US08835220B2Publication Date: 2014-09-16
- Inventor: Huay Huay Sim , Choong Kooi Chee , Kein Fee Liew
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: H01L21/56
- IPC: H01L21/56
Abstract:
In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.
Public/Granted literature
- US20130230946A1 BACKSIDE MOLD PROCESS FOR ULTRA THIN SUBSTRATE AND PACKAGE ON PACKAGE ASSEMBLY Public/Granted day:2013-09-05
Information query
IPC分类:
