公开(公告)号：US11652026B2

公开(公告)日：2023-05-16

申请号：US17587647

申请日：2022-01-28

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US10136516B2

公开(公告)日：2018-11-20

申请号：US15607612

申请日：2017-05-29

Applicant: INTEL CORPORATION

Inventor： Howe Yin Loo ,  Choong Kooi Chee

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/18 ,  H01L23/13 ,  H01L23/367 ,  H01L23/498 ,  H05K3/30 ,  H01L25/065 ,  H05K1/14 ,  H05K3/34 ,  H01L23/427

Abstract: The present description relates to the field of fabricating microelectronic structures. The microelectronic structure may include a microelectronic substrate have an opening, wherein the opening may be formed through the microelectronic substrate or may be a recess formed in the microelectronic substrate. A microelectronic package may be attached to the microelectronic substrate, wherein the microelectronic package may include an interposer having a first surface and an opposing second surface. A microelectronic device may be attached to the interposer first surface and the interposer may be attached to the microelectronic substrate by the interposer first surface such that the microelectronic device extends into the opening. At least one secondary microelectronic device may be attached to the interposer second surface.

公开(公告)号：US20150072474A1

公开(公告)日：2015-03-12

申请号：US14486849

申请日：2014-09-15

Applicant: Intel Corporation

Inventor： Huay Huay Sim ,  Choong Kooi Chee ,  Kein Fee Liew

IPC: H01L21/56 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L21/565 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/20641 ,  H01L2924/3511 ,  H01L2924/401 ,  Y10T29/49002 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.

公开(公告)号：US11805602B2

公开(公告)日：2023-10-31

申请号：US17089736

申请日：2020-11-05

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee ,  Teong Guan Yew

IPC: H05K1/18 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H05K3/34 ,  H05K3/32

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H05K3/323 ,  H05K3/3436 ,  H01L2224/16225 ,  H05K2201/10378 ,  H05K2201/10734 ,  H05K2201/10992

Abstract: A chip assembly may include a package substrate that includes one or more pins. The chip assembly may also include one or more pads. The one or more pads may be electrically coupled to the one or more pins. In addition, the chip assembly may include a board that includes one or more board pads. Further, the chip assembly may include an anisotropic layer. The anisotropic layer may be positioned between the board and the one or more pads and between the board and a portion of the package substrate. In addition, the anisotropic layer may mechanically couple the board to the one or more pads and to the portion of the package substrate. Further, the anisotropic layer may electrically couple the one or more pads to the one or more board pads.

公开(公告)号：US11527481B2

公开(公告)日：2022-12-13

申请号：US17090933

申请日：2020-11-06

Applicant: Intel Corporation

Inventor： Choong Kooi Chee ,  Bok Eng Cheah ,  Teong Guan Yew ,  Jackson Chung Peng Kong ,  Loke Yip Foo

IPC: H01L23/48 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/13 ,  H01L25/18 ,  H01L25/065

Abstract: According to various examples, a device is described. The device may include a package substrate. The device may also include a plurality of semiconductor devices disposed on the package substrate, wherein the plurality of semiconductor devices comprises top surfaces and bottom surfaces. The device may also include a plurality of interconnects coupled to the package substrate, wherein the plurality of interconnects are adjacent to the plurality of semiconductor devices. The device may also include a flyover bridge coupled to the top surfaces of the plurality of semiconductor devices and the plurality of interconnects, wherein the flyover bridge is directly coupled to the package substrate by the plurality of interconnects, and wherein the bottom surfaces of the plurality of semiconductor devices are electrically isolated from the package substrate.

公开(公告)号：US20210391238A1

公开(公告)日：2021-12-16

申请号：US17461459

申请日：2021-08-30

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US08835220B2

公开(公告)日：2014-09-16

申请号：US13776189

申请日：2013-02-25

Applicant: Intel Corporation

Inventor： Huay Huay Sim ,  Choong Kooi Chee ,  Kein Fee Liew

IPC: H01L21/56

CPC classification number: H01L21/565 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/16 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/181 ,  H01L2924/20641 ,  H01L2924/3511 ,  H01L2924/401 ,  Y10T29/49002 ,  Y10T29/49124 ,  H01L2924/00 ,  H01L2924/00012

Abstract: In some embodiments, selective electroless plating for electronic substrates is presented. In this regard, a method is introduced including receiving a coreless substrate strip, forming a stiffening mold on a backside of the coreless substrate strip adjacent to sites where solder balls are to be attached, and attaching solder balls to the backside of the coreless substrate strip amongst the stiffening mold. Other embodiments are also disclosed and claimed.

Abstract translation: 在一些实施例中，提出了用于电子基板的选择性无电镀。 在这方面，引入了一种方法，包括接收无芯基板条，在与无焊基板条的背面相邻的无芯基板条的背面上形成加强模，并将焊球附着到无芯基板条的背面 在加强模具之间。 还公开并要求保护其他实施例。

公开(公告)号：US12080628B2

公开(公告)日：2024-09-03

申请号：US18132801

申请日：2023-04-10

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Wai Ling Lee ,  Tat Hin Tan

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/822 ,  H01L23/00 ,  H01L23/48 ,  H01L25/16 ,  H01L49/02

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L21/8221 ,  H01L24/09 ,  H01L24/17 ,  H01L25/16 ,  H01L28/40

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.

公开(公告)号：US11107751B2

公开(公告)日：2021-08-31

申请号：US16284239

申请日：2019-02-25

Applicant: Intel Corporation

Inventor： Loke Yip Foo ,  Choong Kooi Chee

IPC: H01L23/48 ,  H01L23/00 ,  H01L25/18 ,  H01L23/31 ,  H01L23/538 ,  H01L23/367 ,  H01L21/56

Abstract: Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.

公开(公告)号：US10903142B2

公开(公告)日：2021-01-26

申请号：US16402482

申请日：2019-05-03

Applicant: Intel Corporation

Inventor： Bok Eng Cheah ,  Choong Kooi Chee ,  Jackson Chung Peng Kong ,  Tat Hin Tan ,  Wai Ling Lee

IPC: H01L23/02 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/768 ,  H01L21/822 ,  H01L49/02

Abstract: An electronic device comprises an integrated circuit (IC) die. The IC die includes a first bonding pad surface and a first backside surface opposite the first bonding pad surface; a first active device layer arranged between the first bonding pad surface and the first backside surface; and at least one stacked through silicon via (TSV) disposed between the first backside surface and the first bonding pad surface, wherein the at least one stacked TSV includes a first buried silicon via (BSV) portion having a first width and a second BSV portion having a second width smaller than the first width, and wherein the first BSV portion extends to the first backside surface and the second BSV portion extends to the first active device layer.