发明授权
US08872283B2 Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
有权
集成电路包括交叉耦合晶体管,其具有形成在门级特征布局通道内的栅电极,在双晶体管形成栅极级特征的相对侧具有共享扩散区
- 专利标题: Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with shared diffusion regions on opposite sides of two-transistor-forming gate level feature
- 专利标题(中): 集成电路包括交叉耦合晶体管,其具有形成在门级特征布局通道内的栅电极,在双晶体管形成栅极级特征的相对侧具有共享扩散区
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申请号: US13741305申请日: 2013-01-14
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公开(公告)号: US08872283B2公开(公告)日: 2014-10-28
- 发明人: Scott T. Becker , Jim Mali , Carole Lambert
- 申请人: Tela Innovations, Inc.
- 申请人地址: US CA Los Gatos
- 专利权人: Tela Innovations, Inc.
- 当前专利权人: Tela Innovations, Inc.
- 当前专利权人地址: US CA Los Gatos
- 代理机构: Martine Penilla Group, LLP
- 主分类号: H01L27/088
- IPC分类号: H01L27/088 ; G06F17/50 ; H01L27/092 ; H01L27/02
摘要:
A semiconductor device includes conductive features within a gate electrode level region that are each fabricated from a respective originating rectangular-shaped layout feature having a centerline aligned parallel to a first direction. The conductive features form gate electrodes of first and second PMOS transistor devices, and first and second NMOS transistor devices. The gate electrodes of the first PMOS and first NMOS transistor devices extend along a first gate electrode track. The gate electrodes of the second PMOS and second NMOS transistor devices extend along a second gate electrode track. A first set of interconnected conductors electrically connect the gate electrodes of the first PMOS and second NMOS transistor devices. A second set of interconnected conductors electrically connect the gate electrodes of the second PMOS and first NMOS transistor devices. The first and second sets of interconnected conductors traverse across each other within different levels of the semiconductor device.
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