A PWM duty cycle converter includes a PWM signal generator, a timing signal generator, a limit signal generator, and a duty cycle limiter. The PWM signal generator generates a first PWM signal by comparing a triangular carrier wave with a duty command from a signal source. The timing signal generator generates a timing signal synchronously with at least one of a maximum value and a minimum value of the amplitude of the carrier wave. The limit signal generator generates a limit signal in response to the timing signal. The limit signal sets at least one of an upper limit and a lower limit on a duty cycle of the first PWM signal. The duty cycle limiter combines the first PWM signal and the limit signal to output a second PWM signal having a limited duty cycle.