Invention Grant
US08890735B2 Multi-level sigma-delta ADC with reduced quantization levels 有权
具有降低量化级别的多电平Σ-ΔADC

  • Patent Title: Multi-level sigma-delta ADC with reduced quantization levels
  • Patent Title (中): 具有降低量化级别的多电平Σ-ΔADC
  • Application No.: US14351059
    Application Date: 2012-10-08
  • Publication No.: US08890735B2
    Publication Date: 2014-11-18
  • Inventor: Carlo Pinna
  • Applicant: ST-Ericsson SA
  • Applicant Address: CH Plan-les-Ouates
  • Assignee: ST-Ericsson SA
  • Current Assignee: ST-Ericsson SA
  • Current Assignee Address: CH Plan-les-Ouates
  • Agency: Coats & Bennett, P.L.L.C.
  • Priority: EP11185107 20111013
  • International Application: PCT/EP2012/069818 WO 20121008
  • International Announcement: WO2013/053659 WO 20130418
  • Main IPC: H03M3/00
  • IPC: H03M3/00
Multi-level sigma-delta ADC with reduced quantization levels
Abstract:
A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.
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