Multi-Level Sigma-Delta ADC With Reduced Quantization Levels
    1.
    发明申请
    Multi-Level Sigma-Delta ADC With Reduced Quantization Levels 有权
    具有降低量化水平的多级Σ-ΔADC

    公开(公告)号:US20140247169A1

    公开(公告)日:2014-09-04

    申请号:US14351059

    申请日:2012-10-08

    Applicant: ST-Ericsson SA

    Inventor: Carlo Pinna

    CPC classification number: H03M3/422 H03M3/39 H03M3/424 H03M3/454

    Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

    Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径,其包括计算块,模拟积分器和具有降低量化级别的量化器。 此外,转换器包括反馈路径,其被布置为向计算块提供反馈模拟信号。 直接路径包括具有与反馈路径的第二放大块的增益因子相反的增益因子的第一放大块。 该转换器允许降低量化器的复杂性。

    Multi-level sigma-delta ADC with reduced quantization levels
    2.
    发明授权
    Multi-level sigma-delta ADC with reduced quantization levels 有权
    具有降低量化级别的多电平Σ-ΔADC

    公开(公告)号:US08963755B2

    公开(公告)日:2015-02-24

    申请号:US14351111

    申请日:2012-10-10

    Applicant: ST-Ericsson SA

    Inventor: Carlo Pinna

    CPC classification number: H03M3/30 H03M3/39 H03M3/424 H03M3/454

    Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

    Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径,其包括计算块,模拟积分器,数字积分器和具有降低的量化级别的量化器。 此外,转换器包括反馈路径,其被布置为向计算块提供反馈模拟信号。 反馈模拟信号通过反馈路径和计算块直接在量化器的输入端注入。 该转换器允许降低量化器的复杂性。

    Multi-Level Sigma-Delta ADC With Reduced Quantization Levels
    3.
    发明申请
    Multi-Level Sigma-Delta ADC With Reduced Quantization Levels 有权
    具有降低量化水平的多级Σ-ΔADC

    公开(公告)号:US20140266829A1

    公开(公告)日:2014-09-18

    申请号:US14351111

    申请日:2012-10-10

    Applicant: ST-Ericsson SA

    Inventor: Carlo Pinna

    CPC classification number: H03M3/30 H03M3/39 H03M3/424 H03M3/454

    Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.

    Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径,其包括计算块,模拟积分器,数字积分器和具有降低的量化级别的量化器。 此外,转换器包括反馈路径,其被布置为向计算块提供反馈模拟信号。 反馈模拟信号通过反馈路径和计算块直接在量化器的输入端注入。 该转换器允许降低量化器的复杂性。

    Multi-level sigma-delta ADC with reduced quantization levels
    4.
    发明授权
    Multi-level sigma-delta ADC with reduced quantization levels 有权
    具有降低量化级别的多电平Σ-ΔADC

    公开(公告)号:US08890735B2

    公开(公告)日:2014-11-18

    申请号:US14351059

    申请日:2012-10-08

    Applicant: ST-Ericsson SA

    Inventor: Carlo Pinna

    CPC classification number: H03M3/422 H03M3/39 H03M3/424 H03M3/454

    Abstract: A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The direct path comprises a first amplification block having a gain factor which is the inverse of the gain factor of a second amplification block of the feedback path. The converter allows reduction of the complexity of the quantizer.

    Abstract translation: 多电平Σ-Δ模数转换器使用具有降低量化级别的量化器来提供多电平输出。 转换器包括直接路径,其包括计算块,模拟积分器和具有降低量化级别的量化器。 此外,转换器包括反馈路径,其被布置为向计算块提供反馈模拟信号。 直接路径包括具有与反馈路径的第二放大块的增益因子相反的增益因子的第一放大块。 该转换器允许降低量化器的复杂性。

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