发明授权
- 专利标题: Semiconductor wafer plating bus and method for forming
- 专利标题(中): 半导体晶圆电镀母线及成型方法
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申请号: US13948927申请日: 2013-07-23
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公开(公告)号: US08895409B2公开(公告)日: 2014-11-25
- 发明人: Trent S. Uehling
- 申请人: Trent S. Uehling
- 申请人地址: US TX Austin
- 专利权人: Freescale Semiconductor, Inc.
- 当前专利权人: Freescale Semiconductor, Inc.
- 当前专利权人地址: US TX Austin
- 代理商 Joanna G. Chiu; James L. Clingan, Jr.
- 主分类号: H01L21/301
- IPC分类号: H01L21/301 ; H01L21/445 ; H01L23/58 ; H01L21/768 ; H01L23/00
摘要:
A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.
公开/授权文献
- US20130309860A1 SEMICONDUCTOR WAFER PLATING BUS AND METHOD FOR FORMING 公开/授权日:2013-11-21
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