公开(公告)号：US10533259B2

公开(公告)日：2020-01-14

申请号：US16166198

申请日：2018-10-22

申请人： Rohm and Haas Electronic Materials LLC

发明人： Ravi Pokhrel

IPC分类号： H01L21/445 ,  C25D5/02 ,  C25D3/38 ,  C25D7/00 ,  H01L21/027 ,  H05K3/10 ,  H05K3/18 ,  H05K3/40 ,  H01L23/00 ,  H01L21/768 ,  H01L21/288 ,  C25D5/10 ,  C25D7/12 ,  H05K1/09 ,  H01L23/532

摘要： Copper electroplating compositions which include an imidazole compound enables the electroplating of copper having uniform morphology on substrates. The composition and methods of enable copper electroplating of photoresist defined features. Such features include pillars, bond pads and line space features.

公开(公告)号：US10361313B2

公开(公告)日：2019-07-23

申请号：US15465740

申请日：2017-03-22

申请人： ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

发明人： Doo Hyeb Youn ,  Sun Jin Yun ,  Changbong Yeon ,  Young-Jun Yu

IPC分类号： H01L21/04 ,  H01L29/16 ,  H01L29/24 ,  H01L29/45 ,  H01L29/66 ,  H01L21/445 ,  H01L29/772 ,  H01L29/786 ,  H01L21/4763

摘要： Disclosed are an electronic device and a method of fabricating the same. The method of fabricating an electronic device comprises providing on a substrate a channel layer including a two-dimensional material, providing a metal fiber layer on a first surface of a conductive layer, providing the metal fiber layer on the channel layer, and performing a thermal treatment process to form a junction layer where a portion of the metal fiber layer is covalently bonded to a portion of the channel layer.

公开(公告)号：US20190131410A1

公开(公告)日：2019-05-02

申请号：US15940043

申请日：2018-03-29

申请人： BOE TECHNOLOGY GROUP CO., LTD. ,  HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.

发明人： Guangyao Li ,  Guangcai Yuan ,  Dongfang Wang ,  Jun Wang ,  Qinghe Wang ,  Ning Liu

IPC分类号： H01L29/24 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/84 ,  H01L31/0392 ,  H01L31/032 ,  H01L31/113 ,  H01L29/66 ,  H01L21/02 ,  H01L21/445

CPC分类号： H01L29/24 ,  H01L21/02568 ,  H01L21/445 ,  H01L27/1214 ,  H01L27/1222 ,  H01L27/283 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/84 ,  H01L31/0296 ,  H01L31/032 ,  H01L31/03926 ,  H01L31/1136 ,  H01L51/05

摘要： Provided is a thin film transistor, a production method thereof, and an electronic apparatus. The thin film transistor comprises a substrate, and a gate electrode, a gate insulator layer, a source electrode, a drain electrode and an active layer on the substrate, wherein the active layer comprises a stack of two or more layers of graphene-like two-dimensional semiconductor material. The electronic apparatus comprises the thin film transistor, and may be used as an optical or mechanical sensor.

公开(公告)号：US20180337287A1

公开(公告)日：2018-11-22

申请号：US15520574

申请日：2015-10-20

申请人： CAMBRIDGE ENTERPRISE LIMITED

发明人： Henning SIRRINGHAUS ,  Kal BANGER ,  Vincenzo PECUNIA

IPC分类号： H01L29/786 ,  H01L27/32 ,  H01L29/49 ,  H01L21/02 ,  H01L21/445 ,  H01L29/66 ,  H01L51/05 ,  H01L51/00 ,  H01L27/28 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/78693 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/02565 ,  H01L21/02628 ,  H01L21/445 ,  H01L27/283 ,  H01L27/286 ,  H01L27/3262 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66969 ,  H01L29/78391 ,  H01L29/78696 ,  H01L51/0097 ,  H01L51/052 ,  H01L51/0541 ,  H01L2227/323

摘要： A transistor device comprising an inorganic oxide semiconductor channel having a channel length L and a channel width W between source and drain conductors and capacitively coupled to a gate conductor via an organic polymer dielectric in contact with the inorganic oxide semiconductor channel, wherein the gate voltage required to maintain a constant current of at least X nA between the source and drain conductors over a period of 14 hours while the gate and drain conductors are maintained at the same electric potential, varies by less than 1V, preferably less than about 0.2V; wherein X equals the W/L ratio multiplied by 50.

公开(公告)号：US20180212062A1

公开(公告)日：2018-07-26

申请号：US15328201

申请日：2016-09-14

申请人： Wuhan China Star Optoelectronics Technology Co., Ltd.

发明人： Yingtao XIE

IPC分类号： H01L29/786 ,  H01L29/66 ,  H01L21/445 ,  H01L27/12

CPC分类号： H01L29/78648 ,  H01L21/34 ,  H01L21/445 ,  H01L27/1225 ,  H01L27/1262 ,  H01L27/127 ,  H01L27/1292 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78603 ,  H01L29/78633 ,  H01L29/78693

摘要： The present disclosure relates to a coplanar double gate electrode oxide thin film transistor, includes a substrate, a bottom gate electrode, a first gate electrode insulating layer, a oxide semiconductor layer, a source electrode contact area and a drain electrode contact area, a second gate electrode insulating layer and a top gate electrode, wherein, the upper surface of the substrate is recessed toward the inside of the substrate to form a groove, the bottom gate electrode is formed in the groove, so that the upper surface of the bottom gate electrode and the upper surface of the substrate are in the same horizontal plane. The thin film transistor of the present disclosure has the characteristics of the double gate electrode and the coplanar structure, and is capable of improving the stability of the thin film transistor, optimizing the response speed thereof, and lowering the driving voltage.

公开(公告)号：US20160197172A1

公开(公告)日：2016-07-07

申请号：US14916970

申请日：2014-03-09

申请人： JAPAN SCIENCE AND TECHNOLOGY AGENCY

发明人： Yutaka Majima ,  Toshiharu Teranishi ,  Shuhei Takeshita

IPC分类号： H01L29/76 ,  H01L21/445

CPC分类号： H01L29/7613 ,  B82Y10/00 ,  B82Y30/00 ,  H01L21/445 ,  H01L29/0649 ,  H01L29/0665 ,  H01L29/127 ,  H01L29/41725 ,  H01L31/09

摘要： Art electrode pair enables the performance of a device to be accurately delivered, a method for manufacturing the same. An electrode pair 10, wherein one electrode 12A and the other electrode 12B are provided on the same plane so as to face each other with a gap 17 therebetween, and portions of the one electrode 12A and the oilier electrode 12B facing each other are respectively curved so as to get away from the plane along a direction nearing each other. This electrode pair 10 is manufactured by preparing, as a sample, a substrate on which a pair of seed electrodes is formed with a space therebetween so as to have an initial gap, immersing the sample in an electroless plating solution, changing the electroless plating solution after a lapse of a certain period of time, and adjusting the number of times of changing.

摘要翻译： 艺术电极对能够精确地传送装置的性能，其制造方法。 电极对10，其中一个电极12A和另一个电极12B以相互平行的方式设置在同一平面上，间隙为17，并且一个电极12A和油层电极12B彼此面对的部分分别是弯曲的 以便沿着彼此靠近的方向远离飞机。 该电极对10通过以下方式制作作为样品的基板，其上形成有一定距离的种子电极，以便具有初始间隙，将样品浸入化学镀溶液中，改变化学镀溶液 经过一段时间后，调整变更次数。

公开(公告)号：US09368183B2

公开(公告)日：2016-06-14

申请号：US13938117

申请日：2013-07-09

申请人： NVIDIA CORPORATION

发明人： Leilei Zhang

IPC分类号： H01L21/445 ,  G11C11/34 ,  H05K3/24 ,  H01L21/48 ,  H05K3/06

CPC分类号： G11C11/34 ,  H01L21/48 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L2224/13101 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1434 ,  H01L2924/15311 ,  H05K3/067 ,  H05K3/242 ,  H05K2203/175 ,  H01L2924/00 ,  H01L2924/014 ,  H01L2924/00014

摘要： An integrated circuit package includes a packaging substrate with an electrical connection pad formed thereon and an integrated circuit die coupled to the electrical connection pad. The electrical connection pad includes an electroplated surface finish layer, but does not include an electrical trace configured as a plating tail. Because the electrical connection pad is free of a plating tail, signal degradation caused by the presence of plating tails in the integrated circuit package is avoided.

摘要翻译： 集成电路封装包括其上形成有电连接焊盘的封装衬底和耦合到电连接焊盘的集成电路裸片。 电连接焊盘包括电镀表面光洁度层，但不包括构造为电镀尾部的电迹线。 由于电连接垫没有电镀尾部，所以避免了由集成电路封装中的电镀尾部引起的信号劣化。

公开(公告)号：US20160093743A1

公开(公告)日：2016-03-31

申请号：US14816767

申请日：2015-08-03

申请人： Samsung Display Co., Ltd.

发明人： Bong-Kyun KIM ,  Sang-Won Shin ,  Jong-Hyun Choung

IPC分类号： H01L29/786 ,  H01L29/24 ,  H01L29/45 ,  H01L27/12 ,  H01L29/423 ,  H01L21/445 ,  H01L21/4763 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/7869 ,  H01L21/445 ,  H01L27/124 ,  H01L27/1259 ,  H01L29/24 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66969

摘要： A thin film transistor substrate includes a gate electrode disposed on a substrate; a semiconductor layer partially overlapping the gate electrode, the semiconductor layer including an oxide semiconductor material; a source electrode and a drain electrode disposed on the semiconductor layer, the source electrode and the drain electrode including a barrier layer, a main wiring layer disposed on the barrier layer, and a first capping layer disposed on the main wiring layer and being spaced apart from each other; and second capping layers covering lateral surfaces of the main wiring layers of the source and drain electrodes.

摘要翻译： 薄膜晶体管基板包括设置在基板上的栅电极; 与所述栅电极部分重叠的半导体层，所述半导体层包括氧化物半导体材料; 设置在所述半导体层上的源电极和漏电极，所述源电极和所述漏极包括阻挡层，设置在所述阻挡层上的主布线层以及设置在所述主布线层上并且间隔开的第一覆盖层 从彼此; 以及覆盖源电极和漏电极的主配线层的侧表面的第二覆盖层。

公开(公告)号：US08895409B2

公开(公告)日：2014-11-25

申请号：US13948927

申请日：2013-07-23

申请人： Trent S. Uehling

发明人： Trent S. Uehling

IPC分类号： H01L21/301 ,  H01L21/445 ,  H01L23/58 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L21/76838 ,  H01L23/585 ,  H01L24/05

摘要： A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

摘要翻译： 半导体晶片包括模具，边缘密封件，接合焊盘，电镀母线和迹线。 模具毗邻锯街。 边缘密封沿着管芯的周边，并且包括形成在管芯的最后互连层中的导电层。 接合焊盘形成为最后互连层或最后互连层的一部分上方的金属沉积层的一部分。 电镀巴士在锯街内。 轨迹连接到边缘密封上的接合焊盘和电镀母线（1），与边缘密封绝缘，并形成在金属沉积层中，或（2）通过边缘密封并与边缘密封绝缘。

公开(公告)号：US08574418B2

公开(公告)日：2013-11-05

申请号：US11992372

申请日：2006-09-20

申请人： Hervé Monchoix ,  Frédéric Raynal ,  Jérôme Daviot ,  José Gonzalez

发明人： Hervé Monchoix ,  Frédéric Raynal ,  Jérôme Daviot ,  José Gonzalez

IPC分类号： C25D3/38 ,  C25D5/02 ,  C25D5/18 ,  C25D7/12 ,  C25D11/32 ,  H01L21/288 ,  H01L21/445

CPC分类号： C25D5/54 ,  C25D3/38 ,  C25D5/18 ,  C25D7/123 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76873

摘要： The object of the present invention is a method of coating a surface of a substrate with copper by electroplating. According to the invention, this method comprises: a step during which the surface to be coated is brought into contact with an electroplating bath while the surface is not under electrical bias; a step of forming the coating during which the surface is biased; a step during which the surface is separated from the electroplating bath while it is under electrical bias; the aforementioned electroplating bath comprising, in solution in a solvent: a source of copper ions, with a concentration of between 0.4 and 40mM; and at least one copper complexing agent.

摘要翻译： 本发明的目的是通过电镀用铜涂覆基底表面的方法。 根据本发明，该方法包括：在表面不受电偏压的情况下，待涂覆表面与电镀槽接触的步骤; 形成表面被偏压的涂层的步骤; 其中表面在电位偏压下与电镀浴分离的步骤; 上述电镀浴在溶剂溶液中包含：浓度为0.4至40mM的铜离子源; 和至少一种铜络合剂。