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    PASSIVATED TEST STRUCTURES TO ENABLE SAW SINGULATION OF WAFER
    4.
    发明申请
    PASSIVATED TEST STRUCTURES TO ENABLE SAW SINGULATION OF WAFER 审中-公开
    经过彻底的测试结构，可以实现波形锯齿波

    公开(公告)号：US20130299947A1

    公开(公告)日：2013-11-14

    申请号：US13470448

    申请日：2012-05-14

    申请人： Trent S. Uehling

    发明人： Trent S. Uehling

    IPC分类号： H01L23/544 ,  H01L21/78

    CPC分类号： H01L22/34 ,  G01R31/2884 ,  H01L22/14 ,  H01L22/20 ,  H01L2224/48091 ,  H01L2924/1461 ,  H01L2924/00014 ,  H01L2924/00

    摘要： A wafer having a die area and a scribe street is formed. The die area comprises die circuitry and a plurality of bond pads, and the scribe street comprises a test structure. Circuitry of the test structure is probed, and then a passivation layer overlying the surface of the wafer is formed, the passivation layer overlying the plurality of bond pads and overlying the test structure. Openings in the regions of the passivation layer overlying the plurality of bond pads are then formed to expose the plurality of bond pads while retaining the regions of the passivation layer overlying the test structure until singulation of the wafer. Pad metallizations are formed at the plurality of bond pads via the openings in the regions of the passivation layer and the wafer is singulated. The resulting dies may be packaged and the resulting IC packages may be implemented in electronic devices.

    摘要翻译： 形成具有模具区域和划线路的晶片。 管芯区域包括管芯电路和多个接合焊盘，并且划线路包括测试结构。 探测测试结构的电路，然后形成覆盖晶片表面的钝化层，钝化层覆盖多个接合焊盘并覆盖测试结构。 然后形成覆盖多个接合焊盘的钝化层的区域中的开口以暴露多个接合焊盘，同时保持覆盖测试结构的钝化层的区域，直到晶片的分离。 通过钝化层的区域中的开口在多个接合焊盘处形成焊盘金属化，并且晶片被分割。 所得到的管芯可以被封装，并且所得到的IC封装可以在电子器件中实现。

    SEMICONDUCTOR WAFER PLATING BUS
    5.
    发明申请
    SEMICONDUCTOR WAFER PLATING BUS 有权
    半导体滤波器总线

    公开(公告)号：US20130168830A1

    公开(公告)日：2013-07-04

    申请号：US13343318

    申请日：2012-01-04

    申请人： Trent S. Uehling

    发明人： Trent S. Uehling

    IPC分类号： H01L23/544 ,  H01L21/78

    CPC分类号： H01L21/76838 ,  H01L23/585 ,  H01L24/05

    摘要： A semiconductor wafer includes a die, an edge seal, a bond pad, a plating bus, and trace. The die is adjacent to a saw street. The edge seal is along a perimeter of the die and includes a conductive layer formed in a last interconnect layer of the die. The bond pad is formed as part of metal deposition layer above the last interconnect layer or part of the last interconnect layer. The plating bus is within the saw street. The trace is connected to the bond pad and to the plating bus (1) over the edge seal, insulated from the edge seal, and formed in the metal deposition layer or (2) through the edge seal and insulated from the edge seal.

    摘要翻译： 半导体晶片包括模具，边缘密封件，接合焊盘，电镀母线和迹线。 模具毗邻锯街。 边缘密封沿着管芯的周边，并且包括形成在管芯的最后互连层中的导电层。 接合焊盘形成为最后互连层或最后互连层的一部分上方的金属沉积层的一部分。 电镀巴士在锯街内。 轨迹连接到边缘密封上的接合焊盘和电镀母线（1），与边缘密封绝缘，并形成在金属沉积层中，或（2）通过边缘密封并与边缘密封绝缘。

    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE
    6.
    发明申请
    FUSED BUSS FOR PLATING FEATURES ON A SEMICONDUCTOR DIE 有权
    用于在半导体器件上镀膜特征的熔断母线

    公开(公告)号：US20130023091A1

    公开(公告)日：2013-01-24

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Fused buss for plating features on a semiconductor die
    7.
    发明授权
    Fused buss for plating features on a semiconductor die 有权
    熔融母线用于半导体管芯上的电镀特征

    公开(公告)号：US08349666B1

    公开(公告)日：2013-01-08

    申请号：US13189054

    申请日：2011-07-22

    申请人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    发明人： George R. Leal ,  Kevin J. Hess ,  Trent S. Uehling

    IPC分类号： H01L21/82 ,  H01L21/332 ,  H01L21/44 ,  H01L21/4763

    CPC分类号： H01L23/585 ,  H01L23/5256 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/03001 ,  H01L2224/05556 ,  H01L2224/45124 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/48 ,  H01L2224/03

    摘要： A method for forming a semiconductor structure includes forming a plurality of fuses over a semiconductor substrate; forming a plurality of interconnect layers over the semiconductor substrate and a plurality of interconnect pads at a top surface of the plurality of interconnect layers; and forming a seal ring, wherein the seal ring surrounds active circuitry formed in and on the semiconductor substrate, the plurality of interconnect pads, and the plurality of fuses, wherein each fuse of the plurality of fuses is electrically connected to a corresponding interconnect pad of the plurality of interconnect pads and the seal ring, and wherein when each fuse of the plurality of fuses is in a conductive state, the fuse electrically connects the corresponding interconnect pad to the seal ring.

    摘要翻译： 一种形成半导体结构的方法包括在半导体衬底上形成多个熔丝; 在所述半导体衬底上形成多个互连层，以及在所述多个互连层的顶表面处形成多个互连焊盘; 以及形成密封环，其中所述密封环包围形成在所述半导体衬底上，所述多个互连焊盘和所述多个熔丝中的有源电路，其中所述多个熔丝中的每个熔丝被电连接到相应的互连焊盘 所述多个互连焊盘和所述密封环，并且其中当所述多个熔丝中的每个熔丝处于导通状态时，所述熔丝将相应的互连焊盘电连接到所述密封环。

    Anchored conductive via and method for forming
    8.
    发明授权
    Anchored conductive via and method for forming 有权
    锚固导电通孔和成型方法

    公开(公告)号：US08314026B2

    公开(公告)日：2012-11-20

    申请号：US13029205

    申请日：2011-02-17

    申请人： Trent S. Uehling

    发明人： Trent S. Uehling

    IPC分类号： H01L21/00

    CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/35121 ,  H01L2924/00

    摘要： A conductive via and a method of forming. The conductive via includes a portion located between a conductive contact structure and an overhang portion of a dielectric layer located above the conductive contact structure. In one embodiment, the overhang portion is formed by forming an undercutting layer over the conductive contact structure and then forming a dielectric layer over the conductive contact structure and the undercutting layer. An opening is formed in the dielectric layer and material of the undercutting layer is removed through the opening to create an overhang portion of the dielectric layer. Conductive material of the conductive via is then formed under the overhang portion and in the opening.

    摘要翻译： 导电通孔和成型方法。 导电通孔包括位于导电接触结构和位于导电接触结构之上的电介质层的伸出部分之间的部分。 在一个实施例中，通过在导电接触结构上形成底切层，然后在导电接触结构和底切层上形成电介质层来形成突出部分。 在电介质层中形成开口，并且通过开口去除底切层的材料以形成电介质层的伸出部分。 导电孔的导电材料然后形成在突出部分和开口内。

    Packaged integrated circuit having large solder pads and method for forming
    10.
    发明授权
    Packaged integrated circuit having large solder pads and method for forming 有权
    具有大焊盘的封装集成电路及其形成方法

    公开(公告)号：US08766453B2

    公开(公告)日：2014-07-01

    申请号：US13660243

    申请日：2012-10-25

    申请人： Trent S. Uehling ,  Brett P. Wilkerson

    发明人： Trent S. Uehling ,  Brett P. Wilkerson

    IPC分类号： H01L29/40 ,  H01L23/48 ,  H01L23/52

    CPC分类号： H01L23/49838 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014

    摘要： A package substrate has a die mounted on a first side. One or more inner solder pads are on an inner portion of a second side. A perimeter of the inner portion is aligned with a perimeter of the die. The one or more inner solder pads are the only solder pads on the inner portion. The one or more inner solder pads number no more than five. A plurality of outer solder pads are on an outer portion of the second side. An average of areas of the one or more inner solder pads is at least five times an average of areas of the one or more inner solder pads. The plurality of outer solder ball pads are for receiving solder ball balls. The outer portion is spaced from the perimeter of the inner portion. The outer portion and the inner portion are coplanar.

    摘要翻译： 封装基板具有安装在第一侧上的管芯。 一个或多个内部焊盘位于第二侧的内部。 内部的周边与模具的周边对准。 一个或多个内部焊盘是内部部分上唯一的焊盘。 一个或多个内部焊盘的数量不超过五个。 多个外部焊盘位于第二侧的外侧部分。 所述一个或多个内部焊盘的平均面积至少为所述一个或多个内部焊盘的面积的平均值的五倍。 多个外焊球焊盘用于接收焊球球。 外部部分与内部部分的周边间隔开。 外部和内部是共面的。