Invention Grant
- Patent Title: Chip assembly system
- Patent Title (中): 芯片组装系统
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Application No.: US13765760Application Date: 2013-02-13
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Publication No.: US08896121B2Publication Date: 2014-11-25
- Inventor: Laurent-Luc Chapelon
- Applicant: STMicroelectronics (Crolles 2) SAS
- Applicant Address: FR Crolles
- Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee: STMicroelectronics (Crolles 2) SAS
- Current Assignee Address: FR Crolles
- Agency: Allen, Dyer, Doppelt, Milbrath & Gilchrist, P.A.
- Priority: FR1251362 20120214
- Main IPC: H01L23/492
- IPC: H01L23/492 ; H01L23/00 ; H01L25/065 ; H01L25/00
Abstract:
An assembly of semiconductor wafers/chips wherein the adjacent surfaces of the two wafers/chips comprise an insulating layer having opposite copper pads inserted therein. The insulating layer is made of a material selected from the group including silicon nitride and silicon carbon nitride.
Public/Granted literature
- US20130207268A1 CHIP ASSEMBLY SYSTEM Public/Granted day:2013-08-15
Information query
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