发明授权
- 专利标题: Power budgeting between a processing core, a graphics core, and a bus on an integrated circuit when a limit is reached
- 专利标题(中): 处理核心,图形核心和集成电路总线之间的功率预算,达到极限
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申请号: US13398641申请日: 2012-02-16
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公开(公告)号: US08898494B2公开(公告)日: 2014-11-25
- 发明人: Travis T. Schluessler , Russell J. Fenger
- 申请人: Travis T. Schluessler , Russell J. Fenger
- 申请人地址: US CA Santa Clara
- 专利权人: Intel Corporation
- 当前专利权人: Intel Corporation
- 当前专利权人地址: US CA Santa Clara
- 代理机构: Trop. Pruner & Hu, P.C.
- 主分类号: G06F1/32
- IPC分类号: G06F1/32 ; G06F9/50
摘要:
An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.
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