Invention Grant
- Patent Title: Methods for double-patterning-compliant standard cell design
- Patent Title (中): 符合双重图案的标准电池设计方法
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Application No.: US12702885Application Date: 2010-02-09
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Publication No.: US08907441B2Publication Date: 2014-12-09
- Inventor: Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
- Applicant: Huang-Yu Chen , Yuan-Te Hou , Fung Song Lee , Wen-Ju Yang , Gwan Sin Chang , Yi-Kan Cheng , Li-Chun Tien , Lee-Chung Lu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L21/70
- IPC: H01L21/70 ; H01L27/02 ; H01L23/528 ; H01L27/118
Abstract:
A semiconductor chip includes a row of cells, with each of the cells including a VDD line and a VSS line. All VDD lines of the cells are connected as a single VDD line, and all VSS lines of the cells are connected as a single VSS line. No double-patterning full trace having an even number of G0 paths exists in the row of cells, or no double-patterning full trace having an odd number of G0 paths exists in the row of cells.
Public/Granted literature
- US20110193234A1 Methods for Double-Patterning-Compliant Standard Cell Design Public/Granted day:2011-08-11
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