Invention Grant
US08921233B2 Microelectronic fabrication methods using composite layers for double patterning
有权
使用复合层进行双重图案化的微电子制造方法
- Patent Title: Microelectronic fabrication methods using composite layers for double patterning
- Patent Title (中): 使用复合层进行双重图案化的微电子制造方法
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Application No.: US13241788Application Date: 2011-09-23
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Publication No.: US08921233B2Publication Date: 2014-12-30
- Inventor: Jae-hwang Sim , Min-chul Kim
- Applicant: Jae-hwang Sim , Min-chul Kim
- Applicant Address: KR
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR
- Agency: Myers Bigel Sibley & Sajovec, P.A.
- Priority: KR10-2010-0103057 20101021
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461 ; H01L21/308 ; H01L21/033 ; H01L21/311 ; H01L27/115

Abstract:
Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.
Public/Granted literature
- US20120100706A1 Microelectronic Fabrication Methods Using Composite Layers for Double Patterning Public/Granted day:2012-04-26
Information query
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