A three dimensional (3D) integrated circuit (IC) testing apparatus includes a plurality of connection devices. When a device under test (DUT) such as an interposer or a 3D IC formed by a plurality of 3D dies operates in a testing mode, the 3D IC testing apparatus is coupled to the DUT via a variety of interface channels such as probes. The connection devices and a variety of through silicon vias (TSVs) in the DUT form a TSV chain so that an electrical characteristic test of the variety of TSVs can be tested all at once.