Invention Grant
US08933747B2 Semiconductor chip package including voltage generation circuit with reduced power noise
有权
半导体芯片封装包括具有降低功耗噪声的电压发生电路
- Patent Title: Semiconductor chip package including voltage generation circuit with reduced power noise
- Patent Title (中): 半导体芯片封装包括具有降低功耗噪声的电压发生电路
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Application No.: US13617802Application Date: 2012-09-14
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Publication No.: US08933747B2Publication Date: 2015-01-13
- Inventor: SunWon Kang , Chiwook Kim , Hyun jeong Woo , Sangjoon Hwang
- Applicant: SunWon Kang , Chiwook Kim , Hyun jeong Woo , Sangjoon Hwang
- Applicant Address: KR Suwon-si
- Assignee: SAMSUNG Electronics Co., Ltd.
- Current Assignee: SAMSUNG Electronics Co., Ltd.
- Current Assignee Address: KR Suwon-si
- Agency: Ellsworth IP Group PLLC
- Priority: KR10-2011-0103018 20111010
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G05F3/00 ; H02M1/14 ; H01L23/64 ; G11C11/4074

Abstract:
A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.
Public/Granted literature
- US20130088289A1 SEMICONDUCTOR CHIP PACKAGE INCLUDING VOLTAGE GENERATION CIRCUIT WITH REDUCED POWER NOISE Public/Granted day:2013-04-11
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