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1.发明授权Method of forming external terminals of a package and apparatus for performing the same 有权形成包装的外部端子的方法及其执行方法公开(公告)号：US09113585B2
公开(公告)日：2015-08-18
申请号：US14171992
申请日：2014-02-04
发明人： Yo-Se Eum , Sang-Geun Kim , Seok-Yong Lee
CPC分类号： H05K3/3478 , B23K1/0016 , B23K3/0623 , B23K3/08 , B23K2101/42 , H01L21/4853 , H01L21/6838 , H01L24/11 , H01L2924/0002 , H05K2203/041 , Y10T29/41 , H01L2924/0001
摘要： A method of forming external terminals of a package is provided in which a package substrate may be fixed, an edge portion of the package substrate may be supported to prevent the edge portion of the package substrate from being upwardly bent, a mask having openings may be arranged on the package substrate, and the external terminals may be supplied to the package substrate through the openings of the mask. The supporting portion may downwardly press the edge portion of the package substrate so that the edge portion of the package substrate may not be upwardly bent. As a result, the external terminals on the package substrate may have a uniform thickness.
摘要翻译： 提供一种形成封装的外部端子的方法，其中可以固定封装基板，可以支撑封装基板的边缘部分以防止封装基板的边缘部分向上弯曲，具有开口的掩模可以是 布置在封装衬底上，并且可以通过掩模的开口将外部端子提供给封装衬底。 支撑部分可以向下按压封装基板的边缘部分，使得封装基板的边缘部分不会向上弯曲。 结果，封装基板上的外部端子可以具有均匀的厚度。
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公开(公告)号：US09053978B2
公开(公告)日：2015-06-09
申请号：US13478569
申请日：2012-05-23
申请人： Sang-Wan Nam
发明人： Sang-Wan Nam
IPC分类号： G11C16/04 , H01L27/115 , G11C16/16 , G11C16/34
CPC分类号： G11C16/14 , G11C16/16 , G11C16/26 , G11C16/3445 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582
摘要： An erase system and method of a nonvolatile memory device includes supplying an erase voltage to a plurality of memory cells of a nonvolatile memory, performing a read operation with a read voltage to word lines of the plurality of memory cells, and performing an erase verification operation with an erase verification voltage to at least one of the word lines of the plurality of memory cells, the erase verification voltage lower than the read voltage.
摘要翻译： 非易失性存储器件的擦除系统和方法包括向非易失性存储器的多个存储单元提供擦除电压，对多个存储器单元的字线执行读取电压读取操作，并执行擦除验证操作 具有擦除验证电压至所述多个存储单元中的至少一个字线，所述擦除验证电压低于读取电压。
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公开(公告)号：US09013944B2
公开(公告)日：2015-04-21
申请号：US14064376
申请日：2013-10-28
发明人： Sang Hun Jeon , Cheol Kwon , Yeongkyun Lee
CPC分类号： G11C5/141 , G11C5/147 , G11C29/021 , G11C29/028
摘要： A user system is provided which includes a storage device and an auxiliary power device configured to supply a power to the storage device, wherein the auxiliary power device includes a first one direction device configured to supply a supply voltage from an external power supply to the storage device, a charging unit configured to be charged by the external power supply, a second one direction device configured to selectively supply an output voltage of the charging unit to the storage device, a voltage detector configured to detect a level of the output voltage of the charging unit and to output a first control signal to the storage device, and a switching unit connected between the charging unit and the second one direction device and configured to operate in response to a second control signal from the storage device.
摘要翻译： 提供了一种用户系统，其包括存储装置和被配置为向存储装置供电的辅助电力装置，其中辅助电力装置包括被配置为将来自外部电源的电源电压提供给存储装置的第一单向装置 装置，被配置为由外部电源充电的充电单元，被配置为向存储装置选择性地提供充电单元的输出电压的第二单向装置，被配置为检测所述充电单元的输出电压的电平的电压检测器， 充电单元并将第一控制信号输出到存储装置;以及切换单元，连接在充电单元和第二单向设备之间，并且被配置为响应于来自存储设备的第二控制信号进行操作。
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公开(公告)号：US08947951B2
公开(公告)日：2015-02-03
申请号：US13836902
申请日：2013-03-15
发明人： Sang-Yeop Baeck , Jin-Sung Kim , Jang-Hwan Yoon
CPC分类号： G11C7/12 , G11C5/147 , G11C7/222 , G11C11/419
摘要： A semiconductor memory device includes at least one memory cell connected to an internal voltage line that receives a cell power supply voltage and a write assist circuit connected to the internal voltage line. The write assist circuit lowers a level of the cell power supply voltage to a target level during a first period of a write operation on the memory cell and maintains the level of the cell power supply voltage at the target level during a second period of the write operation based on a write assist control signal. The second period succeeds the first period.
摘要翻译： 半导体存储器件包括连接到接收单元电源电压的内部电压线和连接到内部电压线的写入辅助电路的至少一个存储器单元。 写入辅助电路在存储器单元的写入操作的第一周期期间将单元电源电压的电平降低到目标电平，并且在写入的第二周期期间将单元电源电压的电平维持在目标电平 基于写辅助控制信号进行操作。 第二个时期成为第一个时期。
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5.发明授权公开(公告)号：US08946026B2
公开(公告)日：2015-02-03
申请号：US13238284
申请日：2011-09-21
申请人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
发明人： Sukhun Choi , Boun Yoon , Jae-Jik Baek , Byung-Kwon Cho
IPC分类号： H01L21/8238 , H01L21/3213 , H01L21/28 , H01L29/49 , H01L29/66 , H01L29/78
CPC分类号： H01L21/32139 , H01L21/28088 , H01L21/823842 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： A method of fabricating semiconductor devices having metal gate electrodes includes forming an insulating layer on a semiconductor substrate having a first region and a second region. The insulating layer is formed to include an interlayer insulating layer and a gate insulation layer. The interlayer insulating layer has first and second grooves respectively disposed in the first and second regions, and the gate insulation layer covers at least bottom surfaces of the first and second grooves. A laminated metal layer is formed on the substrate having the insulating layer. A planarization layer having non-photo sensitivity is formed on the laminated metal layer. The planarization layer in the first region is selectively removed using a dry etching process to expose the laminated metal layer in the first region and to form a planarization layer pattern covering the laminated metal layer in the second region.
摘要翻译： 制造具有金属栅电极的半导体器件的方法包括在具有第一区域和第二区域的半导体衬底上形成绝缘层。 绝缘层形成为包括层间绝缘层和栅极绝缘层。 层间绝缘层具有分别设置在第一和第二区域中的第一和第二沟槽，并且栅极绝缘层至少覆盖第一和第二沟槽的至少底表面。 在具有绝缘层的基板上形成层叠金属层。 在层叠金属层上形成具有非光敏性的平坦化层。 使用干蚀刻工艺选择性地去除第一区域中的平坦化层，以暴露第一区域中的层压金属层，并形成覆盖第二区域中的层叠金属层的平坦化图案。
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公开(公告)号：US08934255B2
公开(公告)日：2015-01-13
申请号：US13709635
申请日：2012-12-10
发明人： Hyo-Jae Bang , Jung-Hyeon Kim
摘要： A casing to support a solid state device SSD therein and super capacitors therein to be electronically connected together.
摘要翻译： 用于支撑其中的固态器件SSD的壳体和其中的超级电容器以电子方式连接在一起。
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7.发明授权Semiconductor chip package including voltage generation circuit with reduced power noise 有权半导体芯片封装包括具有降低功耗噪声的电压发生电路公开(公告)号：US08933747B2
公开(公告)日：2015-01-13
申请号：US13617802
申请日：2012-09-14
申请人： SunWon Kang , Chiwook Kim , Hyun jeong Woo , Sangjoon Hwang
发明人： SunWon Kang , Chiwook Kim , Hyun jeong Woo , Sangjoon Hwang
IPC分类号： G11C5/14 , G05F3/00 , H02M1/14 , H01L23/64 , G11C11/4074
CPC分类号： H01L23/642 , G11C11/4074 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor chip package eliminates and minimizes a power noise generated from a voltage generation circuit in the semiconductor chip package includes an integrated circuit chip with a voltage generation circuit that receives an external voltage to generate a supply voltage to be used in an internal circuit and a connection terminal connected to an output node of the voltage generation circuit, and a mounting substrate including a noise eliminator electrically connected to the connection terminal to reduce a power noise of the supply voltage and a mounting substrate to mount the integrated circuit chip to package the integrated circuit chip as the semiconductor chip package.
摘要翻译： 半导体芯片封装消除并最小化半导体芯片封装中的电压产生电路产生的功率噪声包括具有接收外部电压以产生要用于内部电路的电源电压的电压产生电路的集成电路芯片，以及 连接端子连接到电压产生电路的输出节点，以及安装基板，包括电连接到连接端子的噪声消除器，以降低电源电压的功率噪声，以及安装基板以安装集成电路芯片以封装集成 电路芯片作为半导体芯片封装。
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公开(公告)号：US08907391B2
公开(公告)日：2014-12-09
申请号：US13614654
申请日：2012-09-13
申请人： Jung-Soo Nam , Joon-Suk Oh , Hye-Young Park
发明人： Jung-Soo Nam , Joon-Suk Oh , Hye-Young Park
CPC分类号： H01L29/78 , H01L27/0629 , H01L27/0811 , H01L29/66181 , H01L29/94
摘要： A semiconductor device includes a substrate including an active region having an isolated shape and a field region. A gate insulation layer is provided on an upper surface of the active region of the substrate. A gate electrode is provided on the gate insulation layer and spaced apart from the boundary of the active region to cover the middle portion of the active region. An impurity region is provided under a surface of the active region that is exposed by the gate electrode.
摘要翻译： 半导体器件包括具有隔离形状的有源区和场区的衬底。 栅极绝缘层设置在衬底的有源区的上表面上。 栅电极设置在栅绝缘层上并与有源区的边界隔开以覆盖有源区的中间部分。 在由栅电极露出的有源区的表面下方设置有杂质区。
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公开(公告)号：US09177660B2
公开(公告)日：2015-11-03
申请号：US14069588
申请日：2013-11-01
发明人： Hyun-Jun Yoon , Jae-Yong Jeong , Myung-Hoon Choi , Bo-Geun Kim , Ki-Tae Park
CPC分类号： G11C16/26 , G06F11/1048 , G06F11/1072 , G11C16/0483 , G11C29/00
摘要： A method of operating a memory device includes changing a first read voltage, which determines a first voltage state or a second voltage state, to a voltage within a first range and determining the voltage as a first select read voltage, and changing a second read voltage, which is used to determine whether the data stored in the memory cells is a third different voltage state or a fourth different voltage state, to a voltage within a second different range and determining the voltage as a second select read voltage. The first voltage state overlaps the second voltage. The third voltage state overlaps the fourth voltage state. A difference between a voltage at an intersection of the third and fourth voltage states and the second read voltage is greater than a difference between a voltage at an intersection of the first and second voltage states and the first read voltage.
摘要翻译： 一种操作存储器件的方法包括将确定第一电压状态或第二电压状态的第一读取电压改变为第一范围内的电压并将电压确定为第一选择读取电压，并且改变第二读取电压 ，其用于确定存储在存储单元中的数据是否是第三不同电压状态或第四不同电压状态，以及第二不同范围内的电压，并将电压确定为第二选择读取电压。 第一电压状态与第二电压重叠。 第三电压状态与第四电压状态重叠。 第三和第四电压状态的交点处的电压与第二读取电压之间的差异大于第一和第二电压状态与第一读取电压的交点处的电压之间的差。
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公开(公告)号：US09176863B2
公开(公告)日：2015-11-03
申请号：US13415209
申请日：2012-03-08
申请人： Jeong-Beom Seo , Wonmoon Cheon
发明人： Jeong-Beom Seo , Wonmoon Cheon
CPC分类号： G06F12/0246 , G06F3/067 , G06F12/023 , G06F2212/7202
摘要： Described is a memory controller interfacing with a host and a nonvolatile memory. The memory controller may include a buffer unit configured to store an input address table and a first hot address table; and a processing unit configured to judge whether an address from the host coincides with one of addresses stored in the input address table and to store the address from the host in the first hot address table according to the judgment.
摘要翻译： 描述了与主机和非易失性存储器接口的存储器控制器。 存储器控制器可以包括被配置为存储输入地址表和第一热地址表的缓冲单元; 以及处理单元，被配置为根据判断来判断来自主机的地址是否与存储在输入地址表中的地址中的一个地址一致，并且将来自主机的地址存储在第一热地址表中。
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