Invention Grant
- Patent Title: Multi-level sigma-delta ADC with reduced quantization levels
- Patent Title (中): 具有降低量化级别的多电平Σ-ΔADC
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Application No.: US14351111Application Date: 2012-10-10
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Publication No.: US08963755B2Publication Date: 2015-02-24
- Inventor: Carlo Pinna
- Applicant: ST-Ericsson SA
- Applicant Address: CH Plan-les-Ouates
- Assignee: ST-Ericsson SA
- Current Assignee: ST-Ericsson SA
- Current Assignee Address: CH Plan-les-Ouates
- Agency: Coats & Bennett, P.L.L.C.
- Priority: EP11185105 20111013
- International Application: PCT/EP2012/070076 WO 20121010
- International Announcement: WO2013/053769 WO 20130418
- Main IPC: H03M3/00
- IPC: H03M3/00

Abstract:
A multi-level sigma-delta Analog to Digital converter provides multi-level outputs using a quantizer with reduced quantization levels. The converter comprises a direct path comprising a computation block, an analog integrator, a digital integrator and the quantizer with reduced quantization levels. Further, the converter comprises a feedback path arranged to provide to the computation block a feedback analog signal. The feedback analog signal is injected via the feedback path and the computation block directly at the input terminal of the quantizer. The converter allows reduction of the complexity of the quantizer.
Public/Granted literature
- US20140266829A1 Multi-Level Sigma-Delta ADC With Reduced Quantization Levels Public/Granted day:2014-09-18
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